Redundancy in signal distribution trees

1. A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein a signal in subsequent sub trees is driven by a preceding amplifier, wherein the amplifiers are logic gates, which combines the signals of a preferred input connected to a preceding logic gate in the signal path with a signal of a secondary input connected to an adjacent tree path of a neighboring and/or preceding sub tree, wherein the preferred input is connected with protection circuitry that pulls the preferred input to a defined state in case of an interruption of the signal line before the preferred input.

2. The signal distribution tree structure according to claim 1 , wherein said logic gates are 2-way NAND or NOR gates.

3. The signal distribution tree structure according to claim 1 , wherein said protection circuitry comprises a high resistive bleeder/pull-up device connecting a voltage source of a defined level with the preferred input of the logic gate.

4. The signal distribution tree structure according to claim 3 , wherein the high resistive bleeder/pull-up device is a permanently driven transistor whose source is connected to the voltage source of the defined level and whose drain is connected to the preferred input of the logic gate.

5. The signal distribution tree structure according to claim 1 , wherein a level holding device is connected to the preferred input of the logic gate which holds the preferred input at a defined level.

6. The signal distribution tree structure according to claim 5 , wherein the level holding device comprises an inverter, whose input is connected to the preferred input of the logic gate and whose output drives a transistor whose source is connected to the voltage source of the defined level and whose drain is connected to the preferred input of the logic gate.

7. The signal distribution tree structure according to claim 3 , wherein the high resistive bleeder/pull-up device is a transistor whose source is connected to the voltage source of the defined level, whose drain is connected to the preferred input of the logic gate and whose gate is driven by a power-on-reset signal for a period of time until the preferred input of the logic gate is safely driven to the defined level.

8. The signal distribution tree structure according to claim 7 , wherein a signal generation circuit is provided which generates the power-on reset signal (por) until the output of the logic gate switches for the first time from its initial level to another.

9. The signal distribution tree structure according to claim 3 , wherein the high resistive bleeder/pull-up device is a load transistor whose source is connected to the voltage source of a defined first level, whose drain is connected to the preferred input of the logic gate and whose gate is driven by an analyzing circuit.

10. The signal distribution tree structure according to claim 9 , wherein said analyzing circuitry drives the load transistor during a power-on-reset sequence whereby faulty open signal wiring causes pulling of the preferred input of the logic gate to the defined first level whereas correct wiring holds the preferred input on a second level.

11. The signal distribution tree structure according to claim 10 , wherein said analyzing circuitry comprises means to analyze the signal level of the preferred input of the logic gate after the power-on-reset sequence and drives the load transistor permanently in case the preferred input is on the defined first level.

12. The signal distribution tree structure according to claim 1 , wherein said protection circuitry and/or said analyzing circuitry and/or said level holding device is provided at each input of the logic gate.