LED including photonic crystal structure
View Patent ↗A photonic crystal light emitting diode (“PXLED”) is provided. The PXLED includes a periodic structure, such as a lattice of holes, formed in the semiconductor layers of an LED. The parameters of the periodic structure are such that the energy of the photons, emitted by the PXLED, lies close to a band edge of the band structure of the periodic structure. Metal electrode layers have a strong influence on the efficiency of the PXLEDs. Also, PXLEDs formed from GaN have a low surface recombination velocity and hence a high efficiency. The PXLEDs are formed with novel fabrication techniques, such as the epitaxial lateral overgrowth technique over a patterned masking layer, yielding semiconductor layers with low defect density. Inverting the PXLED to expose the pattern of the masking layer or using the Talbot effect to create an aligned second patterned masking layer allows the formation of PXLEDs with low defect density.
1. A method of making a light emitting diode, the method comprising:
providing a substrate;
providing a masking layer overlying said substrate, the masking layer having a planar lattice of openings, wherein a ratio of a period of said planar lattice of openings to a wavelength of said emitted light in air is greater than about 0.1 and less than about 5;
growing a semiconductor structure over the substrate and the masking layer, the semiconductor structure comprising active layer disposed between an n-type region and a p-type region;
removing a portion of the p-type region and the light emitting layer to expose a portion of the n-type region; and
forming a p-electrode on the p-type region and forming an n-electrode on the exposed portion of the n-type region.
2. The method of claim 1 further comprising removing said p-electrode layer at regions corresponding to said planar lattice of openings.
3. The method of claim 1 , wherein said p-electrode layer is reflective.
4. The method of claim 1 , wherein said semiconductor structure comprises a plurality of III-nitride layers.
5. The method of claim 1 further comprising forming a planar lattice of holes in at least said active layer and said p-type region.
6. The method of claim 1 , wherein providing a masking layer having a planar lattice of openings comprises removing portions of said masking layer in a planar lattice of openings with a high resolution lithographic technique.
7. The method of claim 6 , wherein removing portions of said masking layer comprises removing said portions of said masking layer with one of electron beam lithography, nano-imprint lithography, deep X-ray lithography, interferometric lithography, hot embossing, and microcontact printing.
8. The method of claim 1 further comprising forming a planar lattice of holes by a dry etch process.
9. The method of claim 1 wherein forming a p-electrode on the p-type region and forming an n-electrode on the exposed portion of the n-type region comprises forming the p- and n-electrodes on a same side of the semiconductor structure.
10. The method of claim 9 wherein the p- and n-electrodes are formed on a side of the semiconductor structure opposite the substrate.