Design structure for high speed differential receiver with an integrated multiplexer input
View Patent ↗A design structure embodied in a machine readable medium used in a design process includes high-speed interface between a first network component and a second network component, the interface including a positive voltage input (VINP) and a negative voltage input (VINN) for receiving an input data signal from the first network component; the positive voltage input (VINP) coupled to a negative output circuit (OUTN) and the negative voltage input (VINN) by a positive input bus and a negative input bus, the negative voltage input (VINN) also coupled to a positive output circuit (OUTP). Implementing the high-speed interface calls for applying a bias to the a positive input bus and a negative input bus to periodically multiplex a data signal, thus providing a common receiving path for functional data and wrap data of the data signal.
1. A design structure comprising:
a high speed interface for communicating a data signal comprising functional data and wrap data between a first network component and a second network component, the interface comprising a positive voltage input (VINP) coupled to a gate of a positive field effect transistor (PFET) and a gate of an negative field effect transistor (NFET) and a negative voltage input (VINN), coupled to a gate of another positive field effect transistor (PFET) and a gate of another negative field effect transistor (NFET);
a negative output circuit (NFET) comprising a plurality of NFET and a plurality of PFET and a positive output circuit (OUTP) comprising another plurality of NFET and another plurality of PFET;
wherein one of a source and a drain of the PFET in the positive voltage input (VINP) is coupled to a coupling between the NFET in the plurality of NFET and one of a source and a drain of the NFET in the positive voltage input (VINP) is coupled to a coupling between the PFET in the plurality of PFET;
wherein one of a source and a drain of the another PFET in the negative voltage input (VINN) is coupled to a coupling between the NFET in the another plurality of NFET and one of a source and a drain of the another NFET in the negative voltage input (VINN) is coupled to a coupling between the PFET in the another plurality of PFET, wherein, the remaining one of the source and the drain for the another PFET is coupled to the remaining one of the source and the drain for the PFET in the positive voltage input (VINP) to form a positive input bus and the remaining one of the source and the drain for the another NFET is coupled to the remaining one of the source and the drain for the NFET in the positive voltage input (VINP) to form a negative input bus;
wherein a gate for each of the NFET and each of the PFET in the negative output circuit (OUTN) and the positive output circuit (OUTP) are coupled to a common operating point;
wherein the negative output circuit (OUTN) comprises a transmission gate coupled to the common operating point and at least one NFET of the plurality and at least one PFET of the plurality and the positive output circuit (OUTP) comprises another transmission gate coupled to the common operating point and at least one NFET of the another plurality and at least one PFET of the another plurality;
wherein one of a source and a drain for a positive bias device is coupled to the positive input bus and one of a source and a drain for a negative bias device is coupled to the negative input bus; and,
wherein functional data and wrap data from the first network component is submitted to the positive voltage input (VINP) and the negative voltage input (VINN) and passed to the second network component via the negative output circuit (OUTP) and the positive output circuit (OUTP).
2. The design structure of claim 1 , wherein the design structure comprises a netlist describing the high-speed interface.
3. The design structure of claim 1 , wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.
4. The design structure of claim 1 , wherein the design structure includes at least one of test data files, characterization data, verification data, programming data, or design specifications.