Error correction code decoding device
View Patent ↗An error correction code decoding device comprises a first memory having a memory space like a matrix, a first decoding unit writing a first information into the first memory along a first direction, a second decoding unit reading the first information from the first memory along a second direction and a plurality of turbo decoders included in the second decoding unit, and differentiating access timing to a same row or same column with each other.
1. An error correction code decoding device decoding a first coding block based on first information regarding to a decoded result of the first coding block and decoding a second coding block based on second information regarding to a decoded result of the second coding block, the decoding device comprising:
a first memory storing the first information;
a second memory storing the second information;
a first decoding unit coupled to the first and second memories respectively to receive the first coding block, to read the second information from the second memory along a first direction in a memory space of the second memory, to decode the first coding block based on the second information read from the second memory, and to write the first information into the first memory along the first direction in a memory space of the first memory; and
a second decoding unit coupled to the first and second memories respectively to receive a second coding block, to read the first information from the first memory along a second direction being a different direction in the memory space of the first memory, to decode the second coding block based on the first information read from the first memory, and to write the second information into the second memory along the second direction in the memory space of the second memory,
wherein the second decoding unit comprises a first decoder that decodes a first sub-block included in the second coding block and a second decoder that decodes, in partially parallel with the first decoder, a second sub-block included in the second coding block, and
wherein the first decoder starts accessing the first memory to read the first information therefrom and to decode the first sub-block whereas the second decoder starts accessing the first memory later than the first decoder to read the first information therefrom and to decode the second sub-block.
2. The error correction code decoding device according to claim 1 , wherein the memory space of the first memory is divided in to a plurality of divided spaces, the first and second decoders access the plurality of divided spaces.
3. The error correction code decoding device according to claim 1 further comprising:
an interleaving pattern memory which stores an order of reading the first information from the first memory by the second decoding unit.
4. The error correction code decoding device according to claim 2 , further comprising:
a plurality of interleavers setting an access order corresponding to the plurality of divided spaces to the first and second decoders.
5. The error correction code decoding device according to claim 2 , wherein the first and second decoders process the first information read out from the plurality of divided spaces of the first memory by a window unit.
6. The error correction code decoding device according to claim 1 , wherein a forward recursion of the first decoder and a back ward recursion of the second decoder are performed at once.
7. The error correction code decoding device according to claim 1 , wherein the first direction is one of row and column directions in a memory space and the second direction is the other of row and column directions.
8. The error correction code decoding device according to claim 1 , wherein the second decoder starts accessing the first memory one reference clock later than the first decoder.