Apparatus and method for reducing photo leakage current for TFT LCD

1. A method of forming a thin film transistor (TFT) array panel, comprising:

(i) forming a patterned first conductive layer, including a gate line and a shielding portion, on a substrate, the shielding portion being electrically floated;

(ii) forming a gate insulating layer on the patterned first conductive layer and the substrate;

(iii) forming a patterned semiconductor layer, including a portion that overlaps the shielding portion, on the gate insulating layer;

(iv) forming a patterned second conductive layer, including a source electrode and a drain electrode on the patterned semiconductor layer, and a data line electrically connected to the source electrode, wherein the shielding portion is not overlapped with the data line;

(v) forming a patterned passivation layer on the patterned second conductive layer and the substrate; and

(vi) forming a patterned transparent conductive layer on the patterned passivation layer.

2. The method according to claim 1 , wherein the step of forming the patterned first conductive layer further comprises the step of forming a gap between the gate line and the shielding portion.

3. The method according to claim 2 , wherein the width of the gap is less than 6 μm.

4. The method according to claim 1 , wherein the step of forming the patterned first conductive layer comprises the steps of:

(i) forming a first conductive layer on the substrate;

(ii) forming a photo-resist pattern on the first conductive layer;

(iii) etching the first conductive layer by using the photo-resist pattern as a mask to form the gate line and the shielding portion adjacent to the gate line on the substrate; and

(iv) removing the photo-resist pattern.

5. The method according to claim 1 , wherein the step of forming the patterned semiconductor layer comprises the steps of:

(i) forming an intrinsic semiconductor layer on the gate insulating layer;

(ii) forming a doped semiconductor layer on the intrinsic semiconductor layer;

(iii) forming a photo-resist pattern on the doped semiconductor layer;

(iv) etching the intrinsic semiconductor layer and the doped semiconductor layer by using the photo-resist pattern as a mask to form the patterned semiconductor layer; and

(v) removing the photo-resist pattern.

6. The method according to claim 1 , wherein the step of forming the patterned second conductive layer comprises the steps of:

(i) forming a second conductive layer on the doped semiconductor layer and the gate insulating layer;

(ii) forming a photo-resist pattern on the second conductive layer;

(iii) etching the second conductive layer by using the photo-resist pattern as a mask to form the source electrode and the drain electrode on the doped semiconductor layer, and the data line on the gate insulating layer; and

(iv) removing the photo-resist pattern.

7. The method according to claim 1 , wherein the step of forming the patterned passivation layer comprises the steps of:

(i) forming a passivation layer on the patterned second conductive layer and the substrate;

(ii) forming a photo-resist pattern on the passivation layer;

(iii) etching the passivation layer by using the photo-resist pattern as a mask to form a contact hole exposing a portion of the drain electrode; and

(iv) removing the photo-resist pattern.

8. The method according to claim 7 , wherein the step of forming the patterned transparent conductive layer comprises the step of:

(i) forming a transparent conductive layer on the patterned passivation layer;

(ii) forming an additional photo-resist pattern on the transparent conductive layer;

(iii) etching the transparent conductive layer by using the additional photo-resist pattern as a mask to form the patterned transparent conductive layer electrically connected to the drain electrode through the contact hole; and

(iv) removing the additional photo-resist pattern.

9. The method according to claim 1 , wherein the step of forming the patterned first conductive layer further includes forming a shielding line, disposed under the data line.

10. The method according to claim 9 , wherein the steps of forming the patterned semiconductor layer, and forming the patterned second conductive layer are performed by using a half-tone mask or a gray-tone mask.

11. The method according to claim 10 , wherein the steps of forming the patterned semiconductor layer and forming the patterned second conductive layer comprise the steps of:

(i) forming an intrinsic semiconductor layer on the gate insulating layer;

(ii) forming a doped semiconductor layer on the intrinsic semiconductor layer;

(iii) forming a second conductive layer on the doped semiconductor layer;

(iv) forming a photo-resist pattern by using the half-tone mask or the gray-tone mask, on the second conductive layer;

(v) etching the intrinsic semiconductor layer, the doped semiconductor layer, and the second conductive layer by using the photo-resist pattern as a mask to form the patterned semiconductor layer, and the patterned second conductive layer on the patterned semiconductor layer; and

(vi) removing the photo-resist pattern.

12. The method according to claim 1 , further comprising the step of forming a storage capacitor between the gate line and the patterned transparent conductive layer.

13. The method according to claim 1 , wherein the shielding portion is formed to have a width that is at least equal to the width of the source electrode.

14. A thin film transistor array panel formed according to the method of claim 1 .