Boot block features in synchronous serial interface NAND
View Patent ↗Embodiments are provided for protecting boot block space in a NAND memory device connected to a host device via an SPI interface. One such method includes programming a boot block password into the NAND memory device such that the host device is required to provide the boot block password in order to access the boot block space. A counter may be provided to track the number of times the host device provides an incorrect password, permanently locking the boot block space if the counter reaches a predetermined value. A further method includes associating each of various areas of the boot block space with at least one write lock bit, setting the write lock bit to a lock enable or lock disable value, and locking or unlocking an area of the boot block space depending on the value of its associated write lock bit. Areas of the boot block space may include a single boot block page, a single boot block, or a plurality of boot blocks.
1. A method of protecting boot block space in a NAND memory device comprising:
receiving a password from a host device, wherein the received password is stored in a register;
comparing the received password with a boot block password programmed into a non-volatile area of the NAND memory device;
allowing access to the boot block space if the received password matches the boot block password, and denying access to the boot block space if the received password does not match the correct boot block password;
wherein the host device and the NAND memory device are connected via a serial peripheral interface (SPI) and communicate via a SPI bus and an SPI NAND controller; and
wherein the SPI NAND controller is configured to transmit serial in signals from the host device without translation into standard NAND format signals.
2. The method of claim 1 , wherein the boot block password is a 64-bit password.
3. The method of claim 1 , wherein allowing and denying access to the boot block space includes allowing and denying read operations to the boot block space.
4. The method of claim 3 , further comprising returning data stored in the boot block space if read operations to the boot block space are allowed, and returning invalid data if read operations to the boot block space are denied.
5. The method of claim 3 , wherein allowing access further includes allowing write and erase operations to the boot block space, only if the boot block space is not further protected by one or more write lock bits stored in a non-volatile area of the NAND memory device.
6. The method of claim 1 , further comprising:
incrementing a counter if the received password does not match the boot block password;
comparing the value of the counter to a maximum allowed value; and
allowing access to the boot block space if one of the one or more additional passwords matches the boot block password, or rendering the boot block space permanently inaccessible if the value of the counter is equal to the maximum allowed value.
7. The method of claim 6 , further comprising resetting the counter after each time the NAND memory device is power cycled on.
8. The method of claim 1 , wherein the non-volatile area of the NAND memory device into which the boot block password is programmed is configured to be programmed a limited number of times.
9. The method of claim 8 , wherein the non-volatile area of the NAND memory device into which the boot block password is programmed comprises a one-time programmable area of the NAND memory device.
10. A memory system comprising:
a host device;
a NAND memory device connected the host device via a serial peripheral interface, wherein the host device and the NAND memory device communicate via an SPI bus and an SPI NAND controller, and wherein the NAND memory device includes a NAND memory array having a boot block space;
at least one register configured to receive a password from the host device via the SPI bus;
decision logic configured to compare the received password with a programmed boot block password, wherein access to the boot block space is allowed or denied based on the comparison; and
wherein the SPI NAND controller is configured to transmit serial in signals from the host device without translation into standard NAND format signals.
11. The memory system of claim 10 , wherein the boot block password is programmed into a non-volatile area of the NAND memory device.
12. The memory system of claim 10 , further comprising a counter configured to increment in value if the received password does not match the boot block password, wherein the value of the counter is compared to a maximum allowed value, and wherein the NAND memory device is configured to render the boot block space permanently inaccessible if the value of the counter is equal to the maximum allowed value.
13. The memory system of claim 12 , wherein the counter is configured to reset after each time the NAND memory device is power cycled on.
14. The memory system of claim 10 , wherein the boot block password is programmed into a non-volatile area of the NAND memory device, and wherein the non-volatile area is configured to be programmed a limited number of times.
15. The memory system of claim 14 , wherein the non-volatile area of the NAND memory device comprises a one-time programmable area of the NAND memory device.