IP Library Granted Patent US 8,427,235
Granted Patent B2
US 8,427,235 · App. 11/874,182 · Granted Apr 23, 2013

Power-MOSFETs with improved efficiency for multi-channel class-D audio amplifiers and packaging thereof

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Quick Facts
Patent No.
US 8,427,235
App. No.
11/874,182
Granted
Apr 23, 2013
Kind
B2
Abstract

A stereo class-D audio system includes a first die including four monolithically integrated NMOS high-side devices and a second a second die including four monolithically integrated PMOS low-side devices. The audio system also includes a set of electrical contacts for connecting the high and low-side devices to components within the a stereo class-D audio system, the set of electrical contacts including at least one supply contact for connecting the drains of the high-side devices to a supply voltage (V cc ) and at least one ground contact for connecting the drains of the low-side devices to ground, the electrical contacts also including respective contacts for each source of the high and low-side devices allowing the source of each high-side device to be connected to the source of a respective low-side device to form two H-bridge circuits.

Claims (27)

1. A stereo class-D audio system that comprises:

four PMOS high-side devices;

four NMOS low-side devices; where the drain of each high-side device is connected to the drain of a respective low-side device to form four H-bridge circuits with the half-bridge circuits grouped as two half-bridge pairs, each half-bridge circuit having an output node at the drains of its high and low-side devices;

a package containing the two hall-bridge pairs; and

a set of electrical contacts for connecting the class-D audio system to an external circuit, the set of electrical contacts including at least one supply contact and at least one ground contact for each of the two half-bridge pairs, the supply contact of each half-bridge pair connected to the sources of the high-side devices within that half-bridge pair and the ground contact of each half-bridge pair connected to the sources of the low-side devices within that half-bridge pair, the electrical contacts also including at least one output contact for each output node of each half-bridge circuit.

2. The stereo class-D audio system of claim 1 wherein the output nodes of the half-bridge circuits in a first half-bridge pair are connected to the respective input terminals of a speaker.

3. The stereo class-D audio system of claim 1 wherein each of the our PMOS high-side devices and each of the four NMOS low-side devices is a vertical device.

4. The stereo class-D audio system of claim 3 wherein each of the four PMOS high-side devices and each of the four NMOS low-side devices is formed in a separate die.

5. The stereo class-D audio system of claim 4 wherein the high-side and the low-side devices in each of the half-bridge circuits is mounted in common to a separate die pad in a semiconductor package, with the drain contacts of the high-side and low-side devices in each of the half-bridge circuits being attached to the separate die pad.

6. The stereo class-D audio system of claim 5 wherein the output node of each half-bridge circuit comprises one of the separate die pads.

7. The stereo class-D audio system of claim 6 wherein the source contact of each of the PMOS high-side devices in each half-bridge pair is connected to a supply voltage pin with at least one bonding wire.

8. The stereo class-D audio system of claim 7 wherein the source contact of each of the NMOS low-side devices in each half-bridge pair is connected to a ground pin with at least one bonding wire.

9. The stereo class-D audio system of claim 8 wherein each of the high side and low side devices in each half-bridge circuit comprises a gate contact, the gate contact of each device being connected to one of the input terminals of a break-before-make (BBM) buffer.

10. The stereo class-D audio system of claim 9 wherein the BBM buffer is connected to an audio signal processor.

11. A class-D audio system comprising:

a first high-side MOSFET and a first low-side MOSFET connected in a first half-bridge circuit and comprised in a semiconductor package, the first high-side and first low-side MOSFETs being vertical MOSFETs and being formed in first and second semiconductor dice, respectively;

a second high-side MOSFET and a second low-side MOSFET connected in a second hall-bridge circuit and comprised in the semiconductor package the second high-side and second low-side MOSFETs being vertical MOSFETs and being formed in third and fourth semiconductor dice, respectively;

the semiconductor package comprising a first die pad and a second die pad, a drain of the first high-side MOSFET and a drain of the first low-side MOSFET being mounted to the first die pad, a drain of the second high-side MOSFET and a drain of the second low-side MOSFET being mounted to the second die pad, the first die pad comprising a first output node and the second die pad comprising a second output node.

12. The class-D audio system of claim 11 , a source of the first high-side MOSFET and a source of the second high-side MOSFET being connected to a supply voltage via first and second bonding wires, respectively.

13. The class-D audio system of claim 12 , a source of the first low-side MOSFET and a source of the second low-side MOSFET being connected to a circuit ground via third and fourth bonding wires, respectively.

14. The class-D audio system of claim 13 , a gate of the first high-side MOSFET and a gate of the first low-side MOSFET being connected to a first break-before-make (BBM) buffer via fifth and sixth bonding wires, respectively.

15. The class-D audio system of claim 14 , a gate of the second high-side MOSFET and a gate of the second low-side MOSFET being connected to a second BBM buffer via seventh and eighth bonding wires, respectively.

16. The class-D audio system of claim 15 , the first and second BBM buffers being connected to an audio signal processor.

17. The class-D audio system of claim 16 wherein the semiconductor package comprises a plurality of pins, the first die pad being connected to first and second pins, the second die pad being connected to third and fourth pins.

18. The class D audio system of claim 17 , the first and third pins being located on an opposite side of the semiconductor package from the second and fourth pins.

19. The class-D audio system of claim 18 wherein the source of the first high-side MOSFET and the source of the second high-side MOSFET are connected in common to fifth and sixth pins and the source of the first low-side MOSFET and the source of the second low-side MOSFET are connected in common to seventh and eighth pins.

20. The class-D audio system of claim 19 wherein the gates of the first and second high-side MOSFETs and the gates of the first and second low-side MOSFETs are connected to ninth, tenth, eleventh and twelfth pins, respectively.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2025
From: ADVANCED ANALOGIC TECHNOLOGIES INCORPORATED
To: SKYWORKS SOLUTIONS, INC.
Reel/Frame 071234/0320 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2008
From: WILLIAMS, RICHARD K.
To: ADVANCED ANALOGIC TECHNOLOGIES
Reel/Frame 020527/0218 →