Video Processing Data Provisioning

1 . A system for performing response-time compensation on video pixel data, the system comprising:

an output configured to be coupled to a timing controller;

at least one video signal processing module configured to process information relating to pixels in a video frame; and

an interface coupled to at least one of the at least one video signal processing module and to the output and configured to provide current-frame pixel data and prior-frame pixel data to the output substantially concurrently, the current-frame pixel data relating to a pixel at a particular location in a current video frame and the prior-frame pixel data relating to the pixel at the particular location in a prior video frame relative to the current video frame.

2 . The system of claim 1 wherein the prior-frame pixel data correspond to a video frame immediately preceding the current frame.

3 . The system of claim 1 wherein the output is a dual low-voltage differential signaling output and the interface is configured to provide the current-frame pixel data on a first connection of the output and to provide the prior-frame pixel data on a second connection of the output.

4 . The system of claim 1 wherein the interface is configured to interlace the current-frame pixel data and the prior-frame pixel data and to provide the interlaced data to the output at approximately twice a rate at which the timing controller can process data for a single video frame pixel.

5 . The system of claim 1 further comprising a data compressor coupled to at least one of the at least one video processing module and to the interface, the interface being coupled to at least one of the at least one video processing module through the data compressor, wherein the data compressor is configured to compress the prior-frame pixel data to provide compressed prior-frame pixel data that comprise X % of a size of the prior-frame pixel data before compression, and wherein the interface is configured to interlace the compressed prior-frame pixel data and the current-frame pixel data and to provide the interlaced data to the output at approximately (100+X) % of a rate at which the timing controller can process data for a single video frame pixel.

6 . The system of claim 1 comprising computer readable media storing instructions in a hardware description language software.

7 . The system of claim 6 , wherein the instructions comprise at least one of: Verilog hardware description language software, Verilog-A hardware description language software, and VHDL hardware description language software.

8 . A method of processing video signals in a receiver, the method comprising:

receiving incoming video signals;

processing the video signals into frames of pixel data; and

sending current-frame pixel data and prior-frame pixel data toward a timing controller substantially concurrently, the current-frame pixel data indicative of a first excitation of a pixel at a particular location in a current video frame and the prior-frame pixel data indicative of a second excitation of the pixel at the particular location in a prior video frame relative to the current video frame.

9 . The method of claim 8 wherein the prior-frame pixel data correspond to a video frame immediately preceding the current frame.

10 . The method of claim 8 wherein the sending comprises sending the current-frame pixel data on a first connection of a low-voltage differential signaling connection and sending the prior-frame pixel data on a second connection of the low-voltage differential signaling connection.

11 . The method of claim 8 further comprising interlacing the current-frame pixel data and the prior-frame pixel data, wherein the sending comprises sending the interlaced data toward the timing controller at approximately twice a rate at which the timing controller can process data for a single video frame pixel.

12 . The method of claim 8 further comprising:

compressing the prior-frame pixel data to provide compressed prior-frame pixel data that comprise X % of a size of the prior-frame pixel data before compression; and

interlacing the current-frame pixel data and the compressed prior-frame pixel data;

wherein the sending comprises sending the interlaced data toward the timing controller at approximately (100+X) % of a rate at which the timing controller can process data for a single video frame pixel.

13 . A computer readable media storing instructions, said instructions when executed are adapted to:

receive incoming video signals;

process the video signals into frames of pixel data; and

send current-frame pixel data and prior-frame pixel data toward a timing controller substantially concurrently, the current-frame pixel data indicative of a first excitation of a pixel at a particular location in a current video frame and the prior-frame pixel data indicative of a second excitation of the pixel at the particular location in a prior video frame relative to the current video frame.

14 . The system of claim 13 wherein said instructions comprise instructions in a hardware description language software.

15 . The system of claim 14 , wherein the instructions in a hardware description language comprise at least one of: Verilog hardware description language software, Verilog-A hardware description language software, and VHDL hardware description language software.