IP Library Granted Patent US 7,728,268
Granted Patent B2
US 7,728,268 · App. 11/877,318 · Granted Jun 1, 2010

Solid-state imaging device and electronic device

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Quick Facts
Patent No.
US 7,728,268
App. No.
11/877,318
Granted
Jun 1, 2010
Kind
B2
Abstract

A solid-state imaging device including a number of pixels, each of which having a photoelectric converting portion, and which are arranged one-dimensionally or in a two-dimensional matrix. The solid-state imaging device includes a peripheral wiring portion with a multilayer structure provided around at least part of the photoelectric converting portion in each of the number of pixels and a light-shielding interlayer connecting material connecting layers of the multilayer structure to each other at least part of the peripheral wiring portion. The light-shielding interlayer connecting material is capable of reflecting or absorbing visible light.

Claims (29)

1. A solid-state imaging device including a number of pixels arranged one-dimensionally or in a two-dimensional matrix with each pixel having a photoelectric converting portion, said device comprising:

a peripheral wiring portion with a multilayer wiring structure around at least part of the photoelectric converting portion in each of the pixels; and

a light-shielding interlayer connecting material connecting layers of the multilayer structure to each other and on at least part of the peripheral wiring portion,

wherein,

the light-shield interlayer connecting material is capable of reflecting or absorbing visible light wherein crosstalk due to modulation on a substract surface on which the pixels are arranged is suppressed and crosstalk due to modulation in the multilayer wiring structure is suppressed.

2. A solid-state imaging device according to claim 1 , wherein

the peripheral wiring portion is between the photoelectric converting portions of adjacent pixels.

3. A solid-state imaging device according to claim 1 , wherein

the peripheral wiring portion is provided in each of a plurality of places around the photoelectric converting portion.

4. A solid-state imaging device according to claim 1 , wherein

a plurality of the interlayer connecting materials are provided on the peripheral wiring portion.

5. A solid-state imaging device according to claim 1 , wherein

the peripheral wiring portion includes an amplifier circuit portion to convert and transfer charges generated in the photoelectric converting portion.

6. A solid-state imaging device according to claim 1 , wherein

at least one of the interlayer connecting material and the peripheral wiring portion is grounded to a specific potential.

7. A solid-state imaging device according to claim 1 , wherein

the interlayer connecting material is linearly provided the two-dimensional matrix.

8. A solid-state imaging device according to claim 1 , wherein

the pixels are arranged in a two-dimensional matrix,

each of the pixels has a polygonal shape, and

a length of the interlayer connecting material is smaller than a length of a longest side of the polygonal shape.

9. A solid-state imaging device according to claim 1 , wherein

the pixels are arranged in a two-dimensional matrix,

each of the pixels are has a polygonal shape, and

a length of the interlayer connecting material is smaller than a length of a longest diagonal of the polygonal shape.

10. An electronic device including a solid-state imaging device, the solid-state imaging device having a number of pixels arranged one-dimensionally or in a two-dimensional matrix, and each pixel including a photoelectric converting portion,

wherein, the solid-state imaging device comprises:

(a) a peripheral wiring portion with a multilayer wiring structure provided around at least part of the photoelectric converting portion in each of the; and

(b) light-shielding interlayer connecting material connecting layers of the multilayer structure to each other and on at least part of the peripheral wiring portion, the interlayer connecting material capable of reflecting or absorbing visible light wherein crosstalk due to modulation on a substrate surface on which the pixels are arranged is suppressed and crosstalk due to modulation in the multilayer wiring structure is suppressed.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2016
From: SONY CORPORATION
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 040419/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 24, 2007
From: SATO, KIMIHIKO; IIZUKA, TETSUYA
To: SONY CORPORATION
Reel/Frame 020005/0078 →