Buck-Boost Switching Voltage Regulator
A buck-boost switching regulator includes two buck switches and two boost switches. Two ramp voltages VY and VY are generated. The voltage VY is compared to a voltage VEA 1 that is proportional to the output of the switching regulator. This defines the duty cycle of the two buck switches. The voltage VX is compared to a voltage VEA 2 that is inversely proportional to the output of the switching regulator. This defines the duty cycle of the two boost switches. The regulator seamlessly transitions between Buck, Boost and Buck-Boost modes depending on input and output conditions.
1 . A circuit for controlling a buck-boost switching regulator where the switching regulator includes two buck switches and two boost switches, the circuit comprising:
a circuit for generating a periodic ramp voltage VX and a periodic ramp voltage VY where VX and VY having a phase difference of 180 degrees;
an error amplifier for generating a voltage VEA 1 that is proportional to the output of the switching regulator;
an amplifier for generating a voltage VEA 2 that is inversely proportional to VEA 1 ;
a first comparator for comparing the ramp voltage VY to the voltage VEA 1 to generate an output that defines the duty cycle of the buck switches; and
a second comparator for comparing the ramp voltage VX to the voltage VEA 2 to generate an output that defines the duty cycle of the boost switches.
2 . A circuit as recited in claim 1 where the buck switches include a control switch connected between an input node and an inductor and where the first comparator turns the control buck switch OFF whenever the ramp voltage VY exceeds the voltage VEA 1 .
3 . A circuit as recited in claim 1 where the boost switches include a free-wheeling switch connected between an inductor and ground and where the second comparator turns the free-wheeling buck switch ON whenever the ramp voltage VX exceeds the voltage VEA 2 .
4 . A circuit as recited in claim 1 where the amplifier is configured to generate VEA 2 by inverting VEA 1 and adding a voltage offset.
5 . A circuit as recited in claim 4 where the magnitude of the voltage offset is selected to provide three different operating modes including a boost mode where the boost switches have a non-zero duty cycle, a buck mode where the buck switches have a non-zero duty cycle and a buck-boost mode where the boost and buck switches have non-zero duty cycles.
6 . A circuit as recited in claim 1 where the first amplifier generates a pulse width modulated signal with trailing edge modulation to define the duty cycle of the buck switches and where the second amplifier generates a pulse width modulated signal with leading edge modulation to define the duty cycle of the boost switches.
7 . A circuit for controlling a buck-boost switching regulator where the switching regulator includes at least one buck switch and at least one boost switch, the circuit comprising:
a circuit for generating a periodic ramp voltage VX and a periodic ramp voltage VY where VX and VY having a phase difference of 180 degrees;
an error amplifier for generating a voltage VEA 1 that is proportional to the output of the switching regulator;
an amplifier for generating a voltage VEA 2 that is inversely proportional to VEA 1 ;
a first comparator for comparing the ramp voltage VY to the voltage VEA 1 to generate an output that defines the duty cycle of the buck switches; and
a second comparator for comparing the ramp voltage VX to the voltage VEA 2 to generate an output that defines the duty cycle of the boost switches.
8 . A circuit as recited in claim 7 where the first comparator turns the buck switch OFF whenever the ramp voltage VY exceeds the voltage VEA 1 .
9 . A circuit as recited in claim 7 where the second comparator turns the buck switch ON whenever the ramp voltage VX exceeds the voltage VEA 2 .
10 . A circuit as recited in claim 7 where the amplifier is configured to generate VEA 2 by inverting VEA 1 and adding a voltage offset.
11 . A circuit as recited in claim 10 where the magnitude of the voltage offset is selected to provide three different operating modes including a boost mode where the boost switch has a non-zero duty cycle, a buck mode where the buck switch has a non-zero duty cycle and a buck-boost mode where the boost and buck switches have non-zero duty cycles.
12 . A circuit as recited in claim 7 where the first amplifier generates a pulse width modulated signal with trailing edge modulation to define the duty cycle of the buck switches and where the second amplifier generates a pulse width modulated signal with leading edge modulation to define the duty cycle of the boost switches.
13 . A method for operating a buck-boost switching regulator, where the switching regulator includes two buck switches and two boost switches, the method comprising:
generating a ramp voltage VX and a ramp voltage VY where VX and VY having a phase difference of 180 degrees;
generating a voltage VEA 1 that is proportional to the output of the switching regulator;
generating a voltage VEA 2 that is inversely proportional to VEA 1 ;
comparing the ramp voltage VY to the to voltage VEA 1 to generate an output that defines the duty cycle of the two buck switches; and
comparing the ramp voltage VX to the to voltage VEA 2 to generate an output that defines the duty cycle of the two boost switches.
14 . A method as recited in claim 13 where the buck switches include a high-side switch connected between an input node and an inductor and where the method further comprises turning the high-side buck switch OFF whenever the ramp voltage VY exceeds the voltage VEA 1 .
15 . A method as recited in claim 13 where the boost switches include a low-side switch connected between an inductor and ground and where the method further comprises turning the low-side buck switch ON whenever the ramp voltage VX exceeds the voltage VEA 2 .
16 . A method as recited in claim 13 that further comprises generating VEA 2 by inverting VEA 1 and adding a voltage offset.
17 . A method as recited in claim 16 where the magnitude of the voltage offset is selected to provide three different operating modes including a boost mode where the boost switches have a non-zero duty cycle, a buck mode where the buck switches have a non-zero duty cycle and a buck-boost mode where the boost and buck switches have non-zero duty cycles.
18 . A circuit as recited in claim 13 where the output that defines the duty cycle of the two buck switches is a pulse width modulated signal with trailing edge modulation and where the output that defines the duty cycle of the two boost switches is a pulse width modulated signal with leading edge modulation.
19 . A method for operating a buck-boost switching regulator, where the switching regulator includes at least one buck switch and at least one boost switch, the method comprising:
generating a ramp voltage VX and a ramp voltage VY where VX and VY having a phase difference of 180 degrees;
generating a voltage VEA 1 that is proportional to the output of the switching regulator;
generating a voltage VEA 2 that is inversely proportional to VEA 1 ;
comparing the ramp voltage VY to the to voltage VEA 1 to generate an output that defines the duty cycle of the buck switch; and
comparing the ramp voltage VX to the to voltage VEA 2 to generate an output that defines the duty cycle of the boost switch.
20 . A method as recited in claim 19 that further comprises turning the high-side buck switch OFF whenever the ramp voltage VY exceeds the voltage VEA 1 .
21 . A method as recited in claim 19 that further comprises turning the low-side buck switch ON whenever the ramp voltage VX exceeds the voltage VEA 2 .
22 . A method as recited in claim 19 that further comprises generating VEA 2 by inverting VEA 1 and adding a voltage offset.
23 . A method as recited in claim 22 where the magnitude of the voltage offset is selected to provide three different operating modes including a boost mode where the boost switch has a non-zero duty cycle, a buck mode where the buck switch has a non-zero duty cycle and a buck-boost mode where the boost and buck switches have non-zero duty cycles.
24 . A circuit as recited in claim 19 where the output that defines the duty cycle of the two buck switches is a pulse width modulated signal with trailing edge modulation and where the output that defines the duty cycle of the two boost switches is a pulse width modulated signal with leading edge modulation.