System and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor

1. A computer-implementable method for improved data processing in a data processing system, said computer-implementable method comprising:

when a load lookahead mode is activated, determining if a first thread has entered into a sleep mode to become an inactive first thread;

when a first thread enters a sleep mode, activating a hardware thread-assist mode;

copying content of a second architected facility from an active second thread to a corresponding first architected facility in said inactive first thread;

performing at least one speculative load in said load lookahead mode; and

writing results of said at least one speculative load to said first architected facility in said inactive first thread.

2. The computer-implementable method according to claim 1 , wherein said copying further comprises:

copying said content in one processing cycle.

3. The computer-implementable method according to claim 1 , wherein said copying further comprises:

interleaving contents of said first architected facility and said second architected facility in said inactive first thread.

4. The computer-implementable method according to claim 1 , wherein said load lookahead mode is activated in response to processing an instruction that results in an instruction stall.

5. The computer-implementable method according to claim 4 , further comprising:

if said first thread has not entered into said sleep mode, processing instructions subsequent to said instruction stall without saving results of said processing to said first architected facility.

6. The computer-implementable method according to claim 4 , further comprising:

in response to resolving said instruction stall, restarting processing at said instruction that resulted in said instruction stall.

7. A system, comprising:

a system memory; and

a plurality of processors coupled to said system memory, wherein at least one of said plurality of processors

is configured for:

when a load lookahead mode is activated, determining if a first thread has entered into a sleep mode to become an inactive first thread;

when a first thread enters a sleep mode, activating a hardware thread-assist mode;

copying content of a second architected facility from an active second thread to a corresponding first architected facility in said inactive first thread;

performing at least one speculative load in said load lookahead mode; and

writing results of said at least one speculative load to said first architected facility in said inactive first thread.

8. The system according to claim 7 , wherein said copying further includes copying said content in one processing cycle.

9. The system according to claim 7 , wherein said copying further includes interleaving contents of said first architected facility and said second architected facility in said inactive first thread.

10. The system according to claim 7 , wherein said load lookahead mode is activated in response to processing an instruction that results in an instruction stall.

11. The system according to claim 10 , wherein said said at least one processor is further configured for:

if said first thread has not entered into said sleep mode, processing instructions subsequent to said instruction stall without saving results of said processing to said first architected facility.

12. The system according to claim 10 , wherein said said at least one processor is further configured for:

in response to resolving said instruction stall, restarting processing at said instruction that resulted in said instruction stall.

13. A computer-usable storage medium embodying computer program code for implementing a hardware-supported thread assist under load lookahead mechanism for a plurality of processors, said computer-usable storage medium comprising:

program code for, when a load lookahead mode is activated, determining if a first thread has entered into a sleep mode to become an inactive first thread;

program code for, when a first thread enters a sleep mode, activating a hardware thread-assist mode;

program code for copying content of a second architected facility from an active second thread to a corresponding first architected facility in said inactive first thread;

program code for performing at least one speculative load in said load lookahead mode; and

program code for writing results of said at least one speculative load to said first architected facility in said inactive first thread.

14. The computer-usable storage medium according to claim 13 , wherein said program code for copying further comprises program code for:

copying said content in one processing cycle.

15. The computer-usable storage medium according to claim 13 , wherein said program code for copying further comprises program code for:

interleaving contents of said first architected facility and said second architected facility in said inactive first thread.

16. The computer-usable storage medium according to claim 13 , wherein said load lookahead mode is activated in response to processing an instruction that results in an instruction stall.

17. The computer-usable storage medium according to claim 16 , wherein said computer-usable storage medium further comprises program code for:

if said first thread has not entered into said sleep mode, processing instructions subsequent to said instruction stall without saving results of said processing to said first architected facility.

18. The computer-usable storage medium according to claim 16 , wherein said computer-usable storage medium further comprises program code for:

in response to resolving said instruction stall, restarting processing at said instruction that resulted in said instruction stall.