Method and system for reducing volatile DRAM power budget

1. A method, comprising:

refreshing a volatile memory at a refresh rate to avoid loss of data, wherein the refreshing the volatile memory at the refresh rate includes refreshing the volatile memory at the refresh rate while a device operably coupled to the volatile memory is in a standby mode;

detecting defective bits at the refresh rate; and

selecting an error correction code to correct the detected defective bits,

wherein selecting the error correction code is based at least in part on determining one or more failure modes associated with one or more patterns of failing locations corresponding to the detected defective bits at the refresh rate.

2. The method of claim 1 , further comprising:

comparing a number of detected defective bits detected at the refresh rate to a threshold of detected defective bits; and

if the number of detected defective bits is greater than the threshold of detected defective bits, repeating said refreshing and detecting with another refresh rate having a higher frequency than an immediately preceding refresh rate that was employed.

3. The method of claim 2 , further comprising:

if the threshold of detected defective bits is higher than the number of detected defective bits by fewer than a selected number of bits, designating the refresh rate corresponding to the number of detected defective bits as an optimal refresh rate.

4. The method of claim 1 , further comprising:

determining all failure modes corresponding to the detected defective bits at the refresh rate.

5. The method of claim 4 , wherein the selecting the error correction code to correct the detected defective bits includes:

selecting, based on the determined failure modes, an error correction code to correct the detected defective bits.

6. The method of claim 1 ,

wherein the detecting defective bits at the refresh rate includes:

detecting all defective bits at the refresh rate after the device has left the standby mode.

7. The method of claim 6 , wherein the detecting all defective bits at the refresh rate after the device has left the standby mode includes:

detecting all defective bits at the refresh rate after the device has left the standby mode and after the device has entered an active mode.

8. The method of claim 7 , wherein the detecting all defective bits at the refresh rate after the device has left the standby mode and after the device has entered an active mode includes:

detecting all defective bits at the refresh rate associated with a portion of the volatile memory after the device has left the standby mode, entered an active mode, and indicated that a portion of volatile memory having detected defective bits will be accessed.

9. A system, comprising:

a power source;

a volatile memory configured to be refreshed to avoid loss of data, the volatile memory operably coupled to the power source;

a memory management module operably coupled to the volatile memory and configured to refresh the volatile memory at a refresh rate, detect defective bits of the volatile memory in response to said refresh, and select an error correction code to correct the detected defective bits,

wherein the memory management module is further configured to refresh at the refresh rate while a device coupled to the volatile memory is in a standby mode, and

wherein the memory management module is further configured to determine one or more failure modes associated with one or more patterns of failing locations corresponding to the detected defective bits at the refresh rate and to select the error correction code based at least in part on the determined failure modes.

10. The system of claim 9 wherein the memory management module is further configured to:

compare a number of detected defective bits at the refresh rate to a threshold of defective bits, and

if the number of detected defective bits is greater than the threshold number of defective bits, cause the volatile memory to be refreshed at another refresh rate having a higher frequency than an immediately preceding refresh rate that was employed.

11. The system of claim 9 wherein the memory management module is further configured to:

compare a number of detected defective bits at the refresh rate to a threshold number of defective bits, and

if the number of detected defective bits is equal to or less than the threshold number of detected defective bits, designate the refresh rate as an optimal refresh rate.

12. The system of claim 9 wherein the memory management module is further configured to detect the defective bits after the device has left the standby mode.

13. An apparatus, comprising:

first means for storing data; and

second means for refreshing the first means for storing data at a refresh rate to avoid loss of said stored data, for detecting defective bits at the refresh rate, and for selecting an error correction code for correcting the detected defective bits based at least in part on determining one or more failure modes associated with one or more patterns of failing locations corresponding to the detected defective bits at the refresh rate,

wherein for refreshing at the refresh rate, the second means includes means for refreshing at the refresh rate the first means while a device operably coupled to the first means is in a standby mode.

14. The apparatus of claim 13 wherein the second means includes:

means for determining whether a number of detected defective bits at the refresh rate exceeds a threshold number of defective bits; and

means for selecting another refresh rate having a higher frequency than an immediately preceding refresh rate that was employed in response to a determination that the number of detected defective bits exceeds the threshold number of defective bits.

15. The apparatus of claim 13 wherein the second means includes:

means for determining all failure modes corresponding to the detected defective bits at the refresh rate.

16. The apparatus of claim 15 , wherein the second means includes means for selecting, based on the determined failure modes, the error correction code for correcting the detected defective bits.

17. The apparatus of claim 13 , wherein:

for detecting defective bits at the refresh rate, the second means includes means for detecting all defective bits at the refresh rate after the device has left the standby mode.

18. The apparatus of claim 17 , wherein the means for detecting all of the defective bits at the refresh rate after the device has left the standby mode include means for detecting all of the defective bits at the refresh rate after the device has left the standby mode and after the device has entered an active mode.

19. The apparatus of claim 18 , wherein the means for detecting all of the defective bits at the refresh rate after the device has left the standby mode and after the device has entered an active mode includes means for detecting all of the defective bits at the refresh rate associated with a portion of the first means having detected defective bits after the device has left the standby mode, entered an active mode, and indicated that the portion of the first means having detected defective bits will be accessed.

20. An apparatus, comprising:

a memory configured to be refreshed to avoid loss of data; and

a memory management module operably coupled to the memory and configured to refresh the memory at a refresh rate while a device operably coupled to the memory is in a standby mode, detect defective bits of the memory in response to said refresh, and select an error correction code to correct the detected defective bits,

wherein the memory management module is further configured to detect the defective bits after the device coupled to the memory has left the standby mode,

wherein the memory management module is further configured to determine one or more failure modes associated with one or more patterns of failing locations corresponding to the detected defective bits at the refresh rate and to select the error correction code based at least in part on the determined failure modes.

21. The apparatus of claim 20 wherein the memory management module is further configured to refresh at the refresh rate while the device is in the standby mode.

22. The apparatus of claim 20 wherein the memory includes dynamic random access memory (DRAM).