High performance system-on-chip using post passivation process
The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.
1 . An integrated circuit chip comprising:
a silicon substrate;
multiple semiconductor devices in or on said silicon substrate, wherein one of said multiple semiconductor devices comprises a transistor;
a metallization structure over said silicon substrate, wherein said metallization structure is connected to said multiple semiconductor devices, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a dielectric layer between said first and second metal layers;
a passivation layer over said metallization structure and over said dielectric layer,wherein a first passivation opening in said passivation layer exposes a first pad of said metallization structure, and a second passivation opening in said passivation layer exposes a second pad of said metallization structure, wherein said first and second pads are separate from each other, and wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer;
a polymer layer over said passivation layer, wherein said polymer layer has a thickness between 2 and 150 micrometers, and wherein said thickness of said polymer layer is greater than that of said passivation layer and that of said dielectric layer;
a first metal post in said polymer layer, wherein said first metal post is connected to said first pad through said first passivation opening, and wherein said first metal post has a first height and a first transverse dimension, wherein said first height is greater than said first transverse dimension;
a second metal post in said polymer layer, wherein said second metal post is connected to said second pad through said second passivation opening, and wherein said second metal post has a second height and a second transverse dimension, wherein said second height is greater than said second transverse dimension;
a first solder structure over said first metal post, wherein said first solder structure is connected to said first pad through said first metal post;
a second solder structure over said second metal post, wherein said second solder structure is connected to said second pad through said second metal post; and
a discrete electrical component over said first and second solder structures, wherein said discrete electrical component comprises a first contact point and a second contact point, wherein said first contact point is connected to said first pad through said first metal post, and said second contact point is connected to said second pad through said second metal post, wherein a vertical distance between said discrete electrical component and said passivation layer is greater than a thickness of said passivation layer, greater than a thickness of said first pad and greater than a thickness of said second pad.
2 . The integrated circuit chip of claim 1 , wherein said polymer layer comprises polyimide.
3 . The integrated circuit chip of claim 1 , wherein said polymer layer comprises benzocyclobutene (BCB).
4 . The integrated circuit chip of claim 1 , wherein said discrete electrical component comprises a capacitor.
5 . The integrated circuit chip of claim 1 , wherein said discrete electrical component comprises a inductor.
6 . The integrated circuit chip of claim 1 , wherein said discrete electrical component comprises a resistor.
7 . The integrated circuit chip of claim 1 , wherein said metallization structure comprises electroplated copper.
8 . The integrated circuit chip of claim 1 , wherein said first passivation opening has a transverse dimension between 0.5 and 30 micrometers.
9 . The integrated circuit chip of claim 1 , wherein said metallization structure comprises aluminum.
10 . The integrated circuit chip of claim 1 , wherein said said second solder structure has a height greater than a thickness of said passivation layer, greater than a thickness of said first pad and greater than a thickness of said second pad.
11 . An integrated circuit chip comprising:
a silicon substrate;
multiple semiconductor devices in or on said silicon substrate, wherein one of said multiple semiconductor devices comprises a transistor;
a metallization structure over said silicon substrate, wherein said metallization structure is connected to said multiple semiconductor devices, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a dielectric layer between said first and second metal layers;
a passivation layer over said metallization structure and over said dielectric layer, wherein a first passivation opening in said passivation layer exposes a first pad of said metallization structure, and a second passivation opening in said passivation layer exposes a second pad of said metallization structure, wherein said first and second pads are separate from each other, and wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer;
a first metal post connected to said first pad through said first passivation opening, and wherein said first metal post has a first height and a first transverse dimension, wherein said first height is greater than said first transverse dimension;
a second metal post connected to said second pad through said second passivation opening, and wherein said second metal post has a second height and a second transverse dimension, wherein said second height is greater than said second transverse dimension;
a first solder structure over said first metal post, wherein said first solder structure is connected to said first pad through said first metal post;
a second solder structure over said second metal post, wherein said second solder structure is connected to said second pad through said second metal post; and
a discrete electrical component over said passivation layer, wherein said discrete electrical component comprises a first contact point and a second contact point, wherein said first contact point is connected to said first pad through said first solder structure and said first metal post, and said second contact point is connected to said second pad through said second solder structure and said second metal post, wherein a vertical distance between said discrete electrical component and said passivation layer is greater than a thickness of said passivation layer, greater than a thickness of said first pad and greater than a thickness of said second pad, greater than said first height and greater than said second height.
12 . The integrated circuit chip of claim 11 further comprising a polymer layer between said passivation layer and said discrete electrical component, wherein said first and second metal posts are in said polymer layer.
13 . The integrated circuit chip of claim 12 , wherein said polymer layer comprises polyimide.
14 . The integrated circuit chip of claim 12 , wherein said polymer layer comprises benzocyclobutene (BCB).
15 . The integrated circuit chip of claim 11 , wherein said metallization structure comprises electroplated copper.
16 . The integrated circuit chip of claim 11 , wherein said discrete electrical component comprises a capacitor.
17 . The integrated circuit chip of claim 11 , wherein said discrete electrical component comprises a inductor.
18 . The integrated circuit chip of claim 11 , wherein said discrete electrical component comprises a resistor.
19 . The integrated circuit chip of claim 11 , wherein said first passivation opening has a transverse dimension between 0.5 and 30 micrometers.
20 . The integrated circuit chip of claim 11 , wherein said metallization structure comprises aluminum.