Scaleable architecture to support high assurance internet protocol encryption (HAIPE)

1. An Internet Protocol (IP) encryption system, comprising:

a cryptographic unit that processes sensitive data for packet encryption/decryption and data authentication;

a first processing unit comprising a data processor that processes sensitive data and forwards the sensitive data to the cryptographic unit for encryption and data authentication, and a control processor that is separate from the data processor and operative with the cryptographic unit for configuring IP networking functions and distributing network configuration information to the data processor through the cryptographic unit, wherein data processing is separated from management and control functions at the separate control processor; and

a second processing unit that receives encrypted data from the cryptographic unit and processes the encrypted data for IP packet routing, fragmentation and reassembly and receives network configuration information from the management subsystem via the cryptographic unit.

2. The IP encryption system according to claim 1 , wherein said first and second processing units comprise respective red and black side subsystems.

3. The IP encryption system according to claim 1 , wherein said first and second processing units and cryptographic unit are operative together in accordance with an encryption standard.

4. The IP encryption system according to claim 1 , wherein said cryptographic unit comprises a cryptographic processor and a cryptographic accelerator comprising at least one field programmable gate array (FPGA) that extends the processing of sensitive data within the cryptographic processor for applications requiring higher bandwidth and/or customer-unique algorithms.

5. The IP encryption system according to claim 1 , wherein said first processing unit comprises a field programmable gate array (FPGA).

6. The IP encryption system according to claim 5 , wherein said FPGA includes a hard and/or soft macro central processing unit.

7. The IP encryption system according to claim 5 , wherein said FPGA includes an IP Layer hardware accelerator.

8. The IP encryption system according to claim 1 , wherein said second processing unit comprises a field programmable gate array (FPGA).

9. The IP encryption system according to claim 8 , wherein said FPGA contains a hard and/or soft macro central processing unit.

10. The IP encryption system according to claim 8 , wherein said FPGA includes an IP Layer hardware accelerator.

11. The IP encryption system according to claim 1 , wherein processing, management and configuration functions on data received from the cryptographic unit are consolidated within said data processor.

12. The IP encryption system according to claim 1 , wherein each of said first and second processing units support a layered IP protocol stack.

13. A system for processing Internet Protocol (IP) layer data, comprising:

a red side processing subsystem that comprises a data processor that processes sensitive data for IP security functions, and a control processor that is separate from the data processor that configures IP networking functions, wherein data processing is separated from management and control functions at the separate control processor;

a cryptographic unit that receives sensitive data from the red side processing subsystem and processes the sensitive data for packet encryption/decryption and data authentication while receiving network configuration information from the management subsystem; and

a black side processing subsystem that receives encrypted data from the cryptographic unit and processes the encrypted data for IP packet routing, fragmentation and reassembly and receives network configuration information from the management subsystem via the cryptographic unit.

14. The system according to claim 13 , wherein said red and black side processing subsystems are operative together in accordance with an encryption standard.

15. The system according to claim 13 , wherein said cryptographic unit comprises a cryptographic processor and a cryptographic accelerator comprising at least one field programmable gate array (FPGA) that extends the processing of sensitive data within the cryptographic processor for applications requiring higher bandwidth and/or customer-unique algorithms.

16. The system according to claim 13 , wherein said black side processing subsystem comprises an integrated control and data processor wherein processing, management and configuration functions on data received from the cryptographic unit are consolidated within said integrated control and data processor.

17. The system according to claim 13 , wherein said red and black side processing subsystems each support a layered IP protocol stack.

18. A method for encrypting Internet Protocol (IP) layer data, comprising:

processing sensitive data within a data processor;

configuring IP networking functions within a control processor that is separate from the data processor;

forwarding the sensitive data to a cryptographic unit for encryption and data authentication;

distributing network configuration information from the control processor through the cryptographic unit such that data processing is separated from management and control functions at the control processor and divided between the data processor and control processor;

receiving the encrypted data from the cryptographic unit; and

processing the encrypted data for IP packet routing, fragmentation and reassembly while receiving network configuration information from the control processor via the cryptographic unit.

19. The method according to claim 18 , which further comprises encrypting and authenticating sensitive data within a cryptographic unit comprising a cryptographic processor and a cryptographic accelerator comprising at least one field programmable gate array (FPGA) that extends the processing of sensitive data within the cryptographic processor for applications requiring higher bandwidth and/or customer-unique algorithms.

20. The method according to claim 18 , which further comprises processing the sensitive data within a field programmable gate array (FPGA).

21. The method according to claim 20 , wherein said FPGA includes a hard and/or soft macro central processing unit.

22. The method according to claim 20 , wherein said FPGA includes an IP Layer hardware accelerator.

23. The method according to claim 18 , which further comprises processing the encrypted data for IP packet routing, fragmentation and reassembly within a field programmable gate array (FPGA).

24. The method according to claim 23 , wherein said FPGA contains a hard and/or soft macro central processing unit.

25. The method according to claim 23 , wherein said FPGA includes an IP Layer hardware accelerator.