Semiconductor integrated circuit having a latch circuit

1. A semiconductor integrated circuit comprising

a latch circuit; wherein:

the latch circuit comprises a first inverter and a second inverter;

the first inverter comprises a first NMOS transistor and a first PMOS transistor;

the second inverter comprises a second NMOS transistor and a second PMOS transistor;

a relationship of current capability of the first NMOS transistor and the first PMOS transistor is constant when a power-supply voltage becomes less than a specified voltage; and

a relationship of current capability of the second PMOS transistor and the second NMOS transistor is constant when the power-supply voltage becomes less than the specified voltage.

2. The semiconductor integrated circuit of claim 1 ; wherein

the first inverter and the second inverter are both constructed from CMOS transistors;

the current capability of the first NMOS transistor is greater than the current capability of the first PMOS transistor when the power-supply voltage becomes less than the specified voltage; and

the current capability of the second PMOS transistor is greater than the current capability of the second NMOS transistor when the power-supply voltage becomes less than the specified voltage.

3. The semiconductor integrated circuit of claim 1 ; wherein

the first inverter and the second inverter are both constructed from CMOS transistors;

the current capability of the first PMOS transistor is greater than the current capability of the first NMOS transistor when the power-supply voltage becomes less than the specified voltage; and

the current capability of the second NMOS transistor is greater than the current capability of the second PMOS transistor when the power-supply voltage becomes less than the specified voltage.

4. The semiconductor integrated circuit of claim 1 comprising semiconductor integrated circuitry including the data holding circuit, which intentionally sets the data state of the semiconductor integrated circuitry so that the leak current, when idle, becomes small by setting the power-supply voltage of the semiconductor integrated circuitry to less than the specified voltage.

5. A communication apparatus comprising a baseband LSI and an application LSI, wherein at least one of these LSI is constructed from the semiconductor integrated circuit of claim 1 .

6. An information reproduction apparatus comprising a media-signal processing LSI and an error correction and servo processing LSI that performs error correction and servo control, wherein at least one of these LSI is constructed from the semiconductor integrated circuit of claim 1 .

7. An image display apparatus comprising an image and sound processing LSI and a display and sound source control LSI, wherein at least one of these LSI is constructed from the semiconductor integrated circuit of claim 1 .

8. An electronic apparatus comprising a signal processing LSI, wherein the signal processing LSI is constructed from the semiconductor integrated circuit of claim 1 .

9. An electronic control apparatus comprising a control LSI, wherein the control LSI is constructed from the semiconductor integrated circuit of claim 1 .

10. The semiconductor integrated circuit of claim 2 , wherein

at least one of the first NMOS transistor and first PMOS transistor has a gate width such that when the power-supply voltage becomes less than a specified voltage, the current capability of the first NMOS transistor is greater than the current capability of the first PMOS transistor; and

at least one of the second PMOS transistor and second NMOS transistor has a gate width such that when the power-supply voltage becomes less than the specified voltage, the current capability of the second PMOS transistor is greater than the current capability of the second NMOS transistor.

11. The semiconductor integrated circuit of claim 2 , wherein

at least one of the first NMOS transistor and first PMOS transistor has a gate length such that when the power-supply voltage becomes less than a specified voltage, the current capability of the first NMOS transistor is greater than the current capability of the first PMOS transistor; and

at least one of the second PMOS transistor and second NMOS transistor has a gate length such that when the power-supply voltage becomes less than the specified voltage, the current capability of the second PMOS transistor is greater than the current capability of the second NMOS transistor.

12. The semiconductor integrated circuit of claim 2 , wherein

at least one of the first NMOS transistor and first PMOS transistor has a gate oxide film thickness such that when the power-supply voltage becomes less than a specified voltage, the current capability of the first NMOS transistor is greater than the current capability of the first PMOS transistor; and

at least one of the second PMOS transistor and second NMOS transistor has a gate oxide film thickness such that when the power-supply voltage becomes less than the specified voltage, the current capability of the second PMOS transistor is greater than the current capability of the second NMOS transistor.

13. The semiconductor integrated circuit of claim 2 , wherein

at least one of the first NMOS transistor and first PMOS transistor has a threshold voltage such that when the power-supply voltage becomes less than a specified voltage, the current capability of the first NMOS transistor is greater than the current capability of the first PMOS transistor; and

at least one of the second PMOS transistor and second NMOS transistor has a threshold voltage such that when the power-supply voltage becomes less than the specified voltage, the current capability of the second PMOS transistor is greater than the current capability of the second NMOS transistor.

14. The semiconductor integrated circuit of claim 2 further comprising a current source that supplies a specified current to data holding nodes.

15. The semiconductor integrated circuit of claim 3 , wherein

at least one of the first PMOS transistor and first NMOS transistor has a gate width such that when the power-supply voltage becomes less than a specified voltage, the current capability of the first PMOS transistor is greater than the current capability of the first NMOS transistor; and

at least one of the second NMOS transistor and second PMOS transistor has a gate width such that when the power-supply voltage becomes less than the specified voltage, the current capability of the second NMOS transistor is greater than the current capability of the second PMOS transistor.

16. The semiconductor integrated circuit of claim 3 , wherein

at least one of the first PMOS transistor and first NMOS transistor has a gate length such that when the power-supply voltage becomes less than a specified voltage, the current capability of the first PMOS transistor is greater than the current capability of the first NMOS transistor; and

at least one of the second NMOS transistor and second PMOS transistor has a gate length such that when the power-supply voltage becomes less than the specified voltage, the current capability of the second NMOS transistor is greater than the current capability of the second PMOS transistor.

17. The semiconductor integrated circuit of claim 3 , wherein

at least one of the first PMOS transistor and first NMOS transistor has a gate oxide film thickness such that when the power-supply voltage becomes less than a specified voltage, the current capability of the first PMOS transistor is greater than the current capability of the first NMOS transistor; and

at least one of the second NMOS transistor and second PMOS transistor has a gate oxide film thickness such that when the power-supply voltage becomes less than the specified voltage, the current capability of the second NMOS transistor is greater than the current capability of the second PMOS transistor.

18. The semiconductor integrated circuit of claim 3 , wherein

at least one of the first PMOS transistor and first NMOS transistor has a threshold voltage such that when the power-supply voltage becomes less than a specified voltage, the current capability of the first PMOS transistor is greater than the current capability of the first NMOS transistor; and

at least one of the second NMOS transistor and second PMOS transistor has a threshold voltage such that when the power-supply voltage becomes less than the specified voltage, the current capability of the second NMOS transistor is greater than the current capability of the second PMOS transistor.

19. The semiconductor integrated circuit of claim 3 further comprising a current source that supplies a specified current to data holding nodes.

20. The semiconductor integrated circuit of claim 14 , wherein the current source is a resistance element.

21. The semiconductor integrated circuit of claim 14 , wherein the current source is a MOS transistor.

22. The semiconductor integrated circuit of claim 19 , wherein the current source is a resistance element.

23. The semiconductor integrated circuit of claim 19 , wherein the current source is a MOS transistor.

24. A movement apparatus comprising the electronic control apparatus of claim 9 .