Data processing device

1 . A data processing device comprising a main memory for storing therein a plurality of instruction streams and a processor for executing an instruction stream transferred from the main memory,

wherein the processor comprising:

an instruction RAM for storing therein the instruction stream transferred from the main memory;

a location address setting section for setting location addresses on a memory space at which the instruction RAM will be placed in such a manner that location addresses, on the memory space, of the instruction stream stored in the instruction RAM do not coincide with location addresses, on the instruction RAM, of another instruction stream; and

an instruction fetch control section for determining, based on location address information indicating the location addresses set by the location address setting section, a space to be accessed by an instruction fetch access, and, according to result of the determination, making access to either the main memory or the instruction RAM.

2 . The data processing device of claim 1 , wherein the location address setting section is configured so as to set, as the location addresses of the instruction RAM, addresses that are the same as addresses on the main memory from which the instruction stream is transferred.

3 . The data processing device of claim 1 , wherein the location address setting section includes a start address setting register, in which the start address of an area where the instruction RAM will be placed is set, and a memory size setting register in which the capacity of the area where the instruction RAM will be placed is set; and

the location address setting section is configured so as to set the location addresses, on the memory space, of the instruction RAM, in the area starting at the start address set in the start address setting register and having the capacity set in the memory size setting register.

4 . The data processing device of claim 1 , wherein the location address setting section includes a start address setting register, in which the start address of an area where the instruction RAM will be placed is set, and an end address setting register in which the end address of the area where the instruction RAM will be placed is set; and

the location address setting section is configured so as to set the location addresses, on the memory space, of the instruction RAM, in the area extending from the address set in the start address setting register to the address set in the end address setting register.

5 . The data processing device of claim 3 , wherein the location address setting section is configured so as to set the capacity of the instruction RAM, in the memory size setting register.

6 . The data processing device of claim 3 , wherein the location address setting section is configured so as to set the capacity of the instruction stream transferred to the instruction RAM, in the memory size setting register.

7 . The data processing device of claim 4 , wherein the location address setting section is configured so as to set, in the end address setting register, a value obtained by adding the capacity of the instruction RAM to the address set in the start address setting register.

8 . The data processing device of claim 4 , wherein the location address setting section is configured so as to set, in the end address setting register, a value obtained by adding the capacity of the instruction stream transferred to the instruction RAM to the address set in the start address setting register.

9 . The data processing device of claim 1 , wherein a plurality of said instruction RAMs are provided, and

the location address setting section is provided for each of the instruction RAMs in a one-to-one correspondence.

10 . The data processing device of claim 1 , wherein the instruction RAM is divided into at least two memory areas; and

the location address setting section is provided for each of the memory areas in a one-to-one correspondence.