Method of fabricating complementary metal-oxide semiconductor (CMOS) thin film transistor (TFT)
View Patent ↗A method of fabricating a Complementary Metal-Oxide Semiconductor (CMOS) Thin Film Transistor (TFT) using a reduced number of masks includes: forming a buffer layer on the entire surface of a substrate; forming polysilicon and photoresist layers on the entire surface of the substrate having the buffer layer; exposing and developing the photoresist layer to form a first photoresist pattern having a first thickness in a region where a semiconductor layer of a first TFT is to be formed, a second thickness in a region where a channel and a Lightly Doped Drain (LDD) region of a second TFT are to be formed, and a third thickness in a region where source and drain regions of the second TFT are to be formed; etching the polysilicon layer using the first photoresist pattern as a mask to pattern the semiconductor layers of the first and second TFTs; performing a first ashing process on the first photoresist pattern to form a second photoresist pattern where the region having the third thickness has been removed from the first photoresist pattern; implanting a first impurity into the source and drain regions of the second TFT using the second photoresist pattern as a mask; performing a second ashing process on the second photoresist pattern to form a third photoresist pattern where the region having the second thickness has been removed from the first photoresist pattern; and implanting a second impurity into the second TFT using the third photoresist pattern as a mask to perform channel doping on the second TFT.
1. A method of fabricating a Complementary Metal-Oxide Semiconductor (CMOS) Thin Film Transistor (TFT), comprising:
forming a buffer layer on an entire surface of a substrate;
forming a polysilicon layer and a photoresist layer on the entire surface of the substrate having the buffer layer;
exposing and developing the photoresist layer to form a first photoresist pattern having a first thickness in a first region where a semiconductor layer of a first TFT is to be formed, a second thickness in a second region where a channel and a Lightly Doped Drain (LDD) region of a second TFT is to be formed, and a third thickness in a third region where source and drain regions of the second TFT is to be formed;
etching the polysilicon layer using the first photoresist pattern as a mask to form the semiconductor layer of the first TFT and the semiconductor layer of the second TFT;
performing a first ashing process on the first photoresist pattern to form a second photoresist pattern where the third region having the third thickness has been removed from the first photoresist pattern;
implanting a first impurity into the source and drain regions of the second TFT using the second photoresist pattern as a mask;
performing a second ashing process on the second photoresist pattern to form a third photoresist pattern where the second region having the second thickness has been removed from the first photoresist pattern; and
implanting a second impurity into the second TFT using the third photoresist pattern as a mask to perform channel doping on the second TFT.
2. The method according to claim 1 , further comprising:
forming a gate insulating layer on the entire surface of the substrate where the semiconductor layer of the first TFT, the channel-doped semiconductor layer of the first TFT, and the source and drain regions of the second TFT have been formed;
forming a gate electrode of the first TFT overlapping a fourth region where the channel of the first TFT is to be formed over the gate insulating layer, and a gate electrode of the second TFT overlapping a fifth region where the channel of the second TFT layer is to be formed over the gate insulating layer;
implanting a third impurity into the semiconductor layer of the second TFT using the gate electrode of the second TFT as a mask to form the LDD region of the second TFT, and to define the channel of the second TFT;
forming a photoresist pattern entirely covering the semiconductor layer of the second TFT and covering the gate electrode of the first TFT;
implanting a fourth impurity into the first TFT using the photoresist pattern as a mask to form the source and drain regions of the first TFT;
forming an interlayer insulating layer on the entire surface of the substrate where the source and drain regions of the first TFT have been formed;
forming source and drain contact holes exposing the source and drain regions of the first and second TFTs through the gate insulating layer and the interlayer insulating layer; and
forming source and drain electrodes of the first and second TFTs connected to the source and drain regions of the First and second TFTs through the source and drain contact holes.
3. The method according to claim 1 , wherein the second thickness is ⅔ that of the first thickness, and the third thickness is ⅓ that of the first thickness.
4. The method according to claim 1 , wherein a mask is arranged on the entire surface of the substrate having the polysilicon layer and the photoresist layer, the mask having a first black matrix corresponding to the first region where the semiconductor layer of the first TFT is to be formed, a second black matrix corresponding to the second region where the channel and the LDD region of the second TFT are to be formed, and a third black matrix corresponding to the third region where the source and drain regions of the second TFT are to be formed.
5. The method according to claim 4 , wherein the mask comprises the first black matrix having a light-shielding layer formed to a first thickness, the second black matrix having a light-shielding layer formed to a thickness of ⅔ of the first thickness, and the third black matrix having a light-shielding layer formed to a thickness of ⅓ of the first thickness.
6. The method according to claim 4 , wherein the mask comprises the third black matrix having light-shielding slits formed to have a first interval, the second black matrix having light-shielding slits formed to have an interval of ⅔ of the first interval, and the first black matrix having light shielding slits formed to have an interval of ⅓ of the first interval.
7. The method according to claim 2 , wherein the first impurity comprises at least one of phosphorus (P), arsenic (As), antimony (Sb) and bismuth (Bi).
8. The method according to claim 2 , wherein the second impurity comprises phosphorus (P) or boron (B).
9. The method according to claim 2 , wherein the third impurity comprises at least one of phosphorus (P), arsenic (As), antimony (Sb) and bismuth (Bi), and has a lower dosage than that of the first impurity.
10. The method according to claim 2 , wherein the fourth impurity comprises at least one of boron (B), aluminum (Al), gallium (Ga) and indium (In).
11. The method according to claim 1 , wherein the first TFT is formed as a P-channel Metal-Oxide Semiconductor (PMOS) TFT, and the second TFT is formed as an N-channel Metal-Oxide Semiconductor (NMOS) TFT.
12. A method of fabricating a Complementary Metal-Oxide Semiconductor (CMOS) Thin Film Transistor (TFT), comprising:
forming a buffer layer on an entire surface of a substrate;
forming a polysilicon layer and a photoresist layer on the entire surface of the substrate having the buffer layer;
exposing and developing the photoresist layer to form a first photoresist pattern having a first thickness in a first region where a channel and a Lightly Doped Drain (LDD) region of a second TFT is to be formed, a second thickness in a second region where a semiconductor layer of a first TFT is to be formed, and a third thickness in a third region where source and drain regions of the second TFT is to be formed;
etching the polysilicon layer using the first photoresist pattern as a mask to form the semiconductor layer of the first TFT and the semiconductor layer of the second TFT;
performing a first ashing process on the first photoresist pattern to form a second photoresist pattern where the third region having the third thickness has been removed from the first photoresist pattern;
implanting a first impurity into the source and drain regions of the second TFT using the second photoresist pattern as a mask;
performing a second ashing process on the second photoresist pattern to form a third photoresist pattern where the second region having the second thickness has been removed from the first photoresist pattern; and
implanting a second impurity into the first TFT using the third photoresist pattern as a mask to perform channel doping on the first TFT.
13. The method according to claim 12 , further comprising:
forming a gate insulating layer on the entire surface of the substrate where the channel-doped semiconductor layer of the first TFT and the source and drain regions of the second TFT have been formed;
forming a gate electrode of the first TFT overlapping a fourth region where a channel of the first TFT is to be formed over the gate insulating layer, and a gate electrode of the second TFT overlapping a fifth region where the channel of the second TFT is to be formed;
implanting a third impurity into the semiconductor layer of the second TFT using the gate electrode of the second TFT as a mask to form the LDD region of the second TFT and to define the channel of the second TFT;
forming a photoresist pattern entirely covering the semiconductor layer of the second TFT and covering the gate electrode of the first TFT;
implanting a fourth impurity into the first TFT using the photoresist pattern as a mask to form source and drain regions of the first TFT;
forming an interlayer insulating layer on the entire surface of the substrate where the source and drain regions of the first TFT have been formed;
forming source and drain contact holes exposing the source and drain regions of the first and second TFTs through the gate insulating layer and the interlayer insulating layer; and
forming source and drain electrodes of the first and second TFTs connected to the source and drain regions of the first and second TFTs through the source and drain contact holes.
14. The method according to claim 12 , wherein the second thickness is ⅔ that of the first thickness, and the third thickness is ⅓ that of the first thickness.
15. The method according to claim 12 , wherein a mask is arranged on the entire surface of the substrate having the polysilicon layer and the photoresist layer, the mask having a first black matrix corresponding to the first region where the channel and the LDD region of the second TFT are to be formed, a second black matrix in a region corresponding to the second region where the semiconductor layer of the first TFT is to be formed, and a third black matrix in a region corresponding to the third region where the source and drain regions of the second TFT are to be formed.
16. The method according to claim 15 , wherein the mask comprises the first black matrix having a light-shielding layer formed to a first thickness, the second black matrix having a light-shielding layer formed to a thickness of ⅔ of the first thickness, and the third black matrix having a light-shielding layer formed to a thickness of ⅓ of the first thickness.
17. The method according to claim 14 , wherein the mask comprises the third black matrix having light-shielding slits formed to have a first interval, the second black matrix having light-shielding slits formed to have an interval of ⅔ of the first interval, and the first black matrix having light-shielding slits formed to have an interval of ⅓ of the first interval.
18. The method according to claim 12 , wherein the first impurity comprises at least one of phosphorus (P), arsenic (As), antimony (Sb) and bismuth (Bi).
19. The method according to claim 13 , wherein the second impurity comprises phosphorus (P) or boron (B).
20. The method according to claim 13 , wherein the third impurity comprises at least one of phosphorus (P), arsenic (As), antimony (Sb) and bismuth (Bi), and has a lower dosage than that of the first impurity.
21. The method according to claim 13 , wherein the fourth impurity comprises at least one of boron (B), aluminum (Al), gallium (Ga) and indium (In).
22. The method according to claim 12 , wherein the first TFT is formed as a P-channel Metal-Oxide Semiconductor (PMOS) TFT, and the second TFT is formed as an N-channel Metal-Oxide Semiconductor (NMOS) TFT.