IP Library Granted Patent US 7,579,973
Granted Patent B2
US 7,579,973 · App. 11/878,499 · Granted Aug 25, 2009

Analog-to-digital converter

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,579,973
App. No.
11/878,499
Granted
Aug 25, 2009
Kind
B2
Abstract

An analog-digital (A-D) converter for outputting a digital signal corresponding to an analog input signal includes: an upper bit A-D converting section for conducting A-D conversion of the analog input signal and outputting an upper bit portion of the digital signal; a lower bit A-D converting section for conducting A-D conversion of the analog input signal and outputting a lower bit portion of the digital signal; and a majority circuit for sampling an A-D conversion result of the lower bit A-D converting section a plurality of times and determining a value of each of the lower bits by majority operation.

Claims (11)

1. An analog-digital (A-D) converter for outputting a digital signal corresponding to an analog input signal, comprising:

an upper bit A-D converting section for conducting A-D conversion of the analog input signal and outputting an upper bit portion of the digital signal;

a lower bit A-D converting section for conducting A-D conversion of the analog input signal and outputting a lower bit portion of the digital signal;

a majority circuit for sampling an A-D conversion result of the lower bit A-D converting section a plurality of times and determining a value of each of the lower bits by majority operation; and

a variable resistor circuit having a resistance value varying according to digital data for producing a reference voltage, the digital data for producing a reference voltage being produced by adding lower bits having a value “1” to the upper bits, wherein

the variable resistor circuit divides a voltage obtained by D-A conversion of the digital data for producing a reference voltage, and

the lower bit A-D converting section uses the voltage output from the variable resistor circuit as a reference voltage.

2. The A-D converter according to claim 1 , wherein the lower bit A-D converting section is capable of varying a bit length of the lower bits.

3. The A-D converter according to claim 1 , wherein the majority circuit is capable of varying the number of sampling operations.

4. The A-D converter according to claim 3 , wherein the majority circuit varies the number of sampling operations according to a cycle of noise.

5. The A-D converter according to claim 3 , further comprising a number-of-sampling-operations determining circuit for obtaining respective frequencies of “1” and “0” sampled in majority operation, and controlling the number of sampling operations of the majority circuit according to the frequencies.

Assignments (2)
CHANGE OF NAME Recorded Nov 24, 2008
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 021897/0707 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 14, 2008
From: KAWAMOTO, AKIRA; SHIMADA, SHOU
To: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Reel/Frame 021388/0071 →