Integrated circuit chip having non-volatile on-chip memories for providing programmable functions and features
View Patent ↗An integrated circuit chip having programmable functions and features in which one-time programmable (OTP) memories are used to implement a non-volatile memory function, and a method for providing the same. The OTP memories may be based on poly-fuses as well as gate-oxide fuses. Because OTP memories are small, less die area is utilized as compared to metal fuses. Additionally, because OTP memories can be implemented as part of standard complementary metal oxide semiconductor (CMOS) processes, the method is less costly and complex than the use of electrically-erasable programmable read-only memories (E2PROMs).
1. A programmable integrated circuit chip, comprising:
a circuit block configured to perform a function; and
a memory, including a plurality of redundant one-time programmable (OTP) memory banks, wherein one of the OTP memory banks is configured to identify a current bank of the plurality of redundant OTP memory banks that is programmed;
wherein the memory is coupled to the circuit block, the memory being programmed after packaging of the circuit chip;
wherein the circuit block is responsive to a programmed state of the memory to perform the function in one of a plurality of operating modes.
2. The programmable integrated circuit chip of claim 1 , wherein the circuit chip is manufactured using a process selected from the group consisting of a complementary metal oxide semiconductor (CMOS) process, a bipolar process, a BiCMOS process, and a BCDMOS process.
3. The programmable integrated circuit chip of claim 1 , wherein one of the banks of the plurality of redundant OTP memory banks provides additional storage in the instance that the current second bank of the plurality of redundant OTP memory banks is non-functional or is sought to be reprogrammed.
4. The programmable integrated circuit chip of claim 1 , wherein one of the banks of the plurality of redundant OTP memory banks includes an OTP memory cell, wherein the OTP memory cell includes a non-volatile storage element and a fuse element.
5. The programmable integrated circuit chip of claim 4 , wherein the fuse element comprises a gate-oxide fuse element.
6. The programmable integrated circuit chip of claim 4 , wherein the fuse element comprises a poly-fuse element.
7. The programmable integrated circuit chip of claim 1 , further comprising:
an external pin coupled to the memory, whereby data can be written to the memory via the external pin.
8. The programmable integrated circuit chip of claim 1 , wherein the circuit block comprises a reference voltage generator configured to generate a reference voltage and wherein the reference voltage generator is responsive to a programmed state of the memory to alter the level of the reference voltage.
9. The programmable integrated circuit chip of claim 8 , further comprising:
a comparator, wherein the reference voltage generator is configured to generate a bandgap reference voltage to be used by the comparator.
10. The programmable integrated circuit chip of claim 1 , wherein the circuit block comprises a power sequencer configured to generate a sequence of output voltages and wherein the power sequencer is responsive to a programmed state of the memory to alter the sequence of output voltages.
11. The programmable integrated circuit chip of claim 10 , further comprising:
a voltage regulator;
wherein the power sequencer is configured to receive a plurality of voltages from the voltage regulator, wherein the sequence of output voltages comprises the plurality of voltages received from the voltage regulator.
12. The programmable integrated circuit chip of claim 1 , further comprising:
optimization logic coupled to the circuit block and the memory, the optimization logic configured to determine an optimized operating parameter for the circuit block and to store state information relating to the optimized operating parameter in the memory.
13. The programmable integrated circuit chip of claim 12 , wherein the optimized operating parameter is one or more of a voltage level, a frequency, a current, or a charge.
14. A programmable integrated circuit, comprising:
a memory, including a plurality of redundant one-time programmable (OTP) memory banks, wherein one of the OTP memory banks is configured to identify a current bank of the plurality of redundant OTP memory banks that is programmed; and
optimization logic connected to the memory, the optimization logic configured to determine an optimized operating parameter for a device external to the programmable integrated circuit and to store state information relating to the optimized operating parameter in the memory for subsequent access by the external device.
15. The programmable integrated circuit chip of claim 14 , wherein the optimized operating parameter is one or more of a voltage level, a frequency, a current, or a charge.
16. A method for operating a programmable integrated circuit chip that includes a memory, comprising:
programming a first one-time programmable (OTP) memory bank of the memory after packaging of the circuit chip;
configuring a second OTP memory bank to identify the first memory bank; and
performing a function within the programmable integrated circuit chip in one of a plurality of operating modes in response to a programmed state of the first OTP memory bank.
17. The method of claim 16 , wherein programming the first OTP memory bank comprises programming an OTP memory cell, wherein the OTP memory cell comprises a fuse element and a storage element.
18. The method of claim 17 , wherein programming the OTP memory cell comprises blowing the fuse element within the OTP memory cell.
19. The method of claim 18 , wherein blowing the fuse element within the OTP memory cell comprises blowing a gate-oxide fuse element within the OTP memory cell.
20. The method of claim 18 , wherein blowing the fuse element within the OTP memory cell comprises blowing a poly-fuse element within the OTP memory cell.
21. The method of claim 16 , wherein programming the first OTP memory bank comprises performing a memory write operation via an external pin of the programmable integrated circuit chip.
22. The method of claim 16 , wherein performing a function within the programmable integrated circuit chip in one of a plurality of operating modes in response to the programmed state of the memory comprises generating a reference voltage wherein the level of the reference voltage is determined based on the programmed state of the first OTP memory bank.
23. The method of claim 16 , wherein performing a function within the programmable integrated circuit chip in one of a plurality of operating modes in response to the programmed state of the memory comprises generating a sequence of output voltages wherein the sequence is determined based on the programmed state of the first OTP memory bank.
24. The method of claim 16 , wherein performing a function within the programmable integrated circuit chip in one of a plurality of operating modes in response to the programmed state of the memory comprises generating one of a frequency, a current, or a charge based on the programmed state of the first OTP memory bank.
25. The method of claim 16 , further comprising:
determining an optimized operating parameter for performing the function within the programmable integrated circuit chip;
wherein programming the first OTP memory bank after packaging of the circuit chip comprises storing state information relating to the optimized parameter in the first OTP memory bank.
26. The method of claim 25 , wherein determining an optimized operating parameter comprises determining one or more of a voltage level, a frequency, a current, or a charge.
27. A method for operating a programmable integrated circuit chip that includes a memory, comprising:
determining an optimized operating parameter for the performance of a function by a device external to the programmable integrated circuit chip;
storing state information relating to the optimized operating parameter in a first one-time programmable (OTP) memory bank after packaging of the circuit chip for subsequent access by the external device; and
configuring a second OTP memory bank to identify the first OTP memory bank as being programmed.
28. The method of claim 27 , wherein determining an optimized operating parameter comprises determining one or more of a voltage level, a frequency, a current, or a charge.
29. The method of claim 27 , wherein the current redundant OTP memory bank provides additional storage in the instance that the first OTP memory bank is non-functional or is sought to be reprogrammed.
30. The method of claim 27 , further comprising:
programming a third OTP memory bank if the first OTP memory bank becomes non-functional or is sought to be reprogrammed.