Data processing device
View Patent ↗A data processing device has an instruction decoder ( 1 ), a control logic unit ( 3 ), and ALU ( 4 ). The instruction decoder ( 1 ) decodes instruction codes of an arithmetic instruction. The control logic unit ( 3 ) detects the effective data width of operation data to be processed according to the decode result from the instruction decoder ( 1 ) and determines the number of cycles for the instruction execution corresponding to the effective data width. The ALU ( 4 ) executes the instruction with the number of cycles of the instruction execution determined by the control logic unit ( 3 ).
1. A data processing device comprising:
an instruction decoder for decoding an instruction code in an arithmetic instruction;
a controller for detecting an effective data width of operation data to be processed for the arithmetic instruction based on the operation data and the decode result from the instruction decoder, and for determining an instruction execution cycle number which is the number of cycles of the execution of the instruction corresponding to the effective data width detected; and
an arithmetic operation unit for executing the arithmetic instruction with the number of cycles for the instruction execution determined by the controller,
wherein the instruction code of the arithmetic instruction includes instruction code information to control the instruction execution cycle number,
wherein whether the effective data width of the operation data is determined on the basis of the operation data is specified as the instruction code information, and
wherein whether instruction code information included in the instruction code is valid, is specified as process setting information.
2. The data processing device as claimed in claim 1 , wherein the controller sets a predetermined data width as the effective data width of the operation data when the process setting information includes information not to detect the effective data width and the instruction code information is valid, and determines the instruction execution cycle number corresponding to the effective data width set as the predetermined data width.