IP Library Granted Patent US 7,642,595
Granted Patent B2
US 7,642,595 · App. 11/878,850 · Granted Jan 5, 2010

Nonvolatile semiconductor memory and method of fabrication thereof

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Quick Facts
Patent No.
US 7,642,595
App. No.
11/878,850
Granted
Jan 5, 2010
Kind
B2
Abstract

There are provided a nonvolatile semiconductor memory of a structure in which electric signals from peripheral circuits are reliably transferred to control gates via word lines even if contact holes cannot be opened accurately above the word lines, and a method of fabricating the nonvolatile semiconductor memory. Plural word lines and plural bit lines are disposed on a semiconductor substrate, and there are memory cells at intersecting portions of the word lines and the bit lines. At contact portions of the word lines and metal wires of an upper layer, polysilicon regions, which include the contact portions, are formed beneath a polysilicon forming the word lines, as an etching stop layer at a time of forming contacts.

Claims (14)

1. A nonvolatile semiconductor memory, comprising:

a plurality of metal wires for connecting to a peripheral circuit of the nonvolatile semiconductor memory;

a semiconductor substrate;

a first insulating film formed on the semiconductor substrate;

an etching stop layer formed on the first insulating film;

a second insulating film formed on the etching stop layer; and

a conductive film formed on the second insulating film, the conductive film forming a plurality of word lines, wherein

the metal wires are connected to the word lines through a plurality of contact portions of the word lines, and

the etching stop layer covers and surrounds the plurality of contact portions of the word lines in a plan view.

2. The nonvolatile semiconductor memory of claim 1 , wherein the etching stop layer is formed of a same material as floating gates of the memory cells.

3. The nonvolatile semiconductor memory of claim 2 , wherein the etching stop layer is a first polysilicon film.

4. The nonvolatile semiconductor memory of claim 3 , wherein the etching stop layer is of a shape of a rectangle, and respective sides of the rectangle are formed so as to be separated by predetermined distances from the contact portion as seen in the plan view.

5. The nonvolatile semiconductor memory of claim 2 wherein the etching stop layer is of a shape of a rectangle, and respective sides of the rectangle are formed so as to be separated by predetermined distances from the contact portion as seen in the plan view.

6. The nonvolatile semiconductor memory of claim 1 , wherein the etching stop layer is of a shape of a rectangle, and respective sides of the rectangle are formed so as to be separated by predetermined distances from the contact portion as seen in the plan view.

Assignments (3)
CHANGE OF NAME Recorded Mar 21, 2014
From: OKI SEMICONDUCTOR CO., LTD
To: LAPIS SEMICONDUCTOR CO., LTD.
Reel/Frame 032495/0483 →
CHANGE OF NAME Recorded Jan 22, 2009
From: OKI ELECTRIC INDUSTRY CO., LTD.
To: OKI SEMICONDUCTOR CO., LTD.
Reel/Frame 022162/0669 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2007
From: SETO, MASARU
To: OKI ELECTRIC INDUSTRY CO., LTD.
Reel/Frame 019669/0964 →