Semiconductor device and manufacturing method thereof

1. A method for manufacturing a semiconductor device, comprising:

forming a device isolation layer in a semiconductor substrate;

forming a gate insulating layer and a gate electrode on the semiconductor substrate;

depositing a triple layer over the resulting structure, the triple layer including a bottom oxide layer, a nitride layer, and a top oxide layer; and

etching the top oxide layer and nitride layer of the triple layer by a first etching process having an etch selectivity of 3:1 or lower, and subsequently removing a remaining portion of the nitride layer by a second process having an etch selectivity of at least 10:1, thereby exposing the bottom oxide layer remaining on the device isolation layer, to form spacers.

2. The method according to claim 1 , wherein forming the device isolation layer comprises:

forming a trench in the semiconductor substrate; and

filling the trench with an oxide layer.

3. The method according to claim 1 , wherein the first etching process (the top oxide layer and nitride layer) comprises etching the top oxide layer in a first step and etching the nitride layer in a second step.

4. The method according to claim 1 , wherein the first etching process is carried out in an etching apparatus having a gap between a top electrode and a bottom electrode in the range of 20-40 mm, an internal reaction chamber pressure in the range of 100-150 mT, and a power supply of 200-250 W.

5. The method according to claim 4 , wherein the first etching process comprises supplying Cl 2 at a flow rate in the range of 80-150 sccm, HBr at a flow rate in the range of 10-50 sccm, and O 2 at a flow rate in the range of 0-20 sccm.

6. The method according to claim 1 , wherein the first etching process determines an etch stop point using a characteristic of a CN compound generated in etching the nitride layer.

7. The method according to claim 1 , wherein the second process is carried out in an etching apparatus having a gap between a top electrode and a bottom electrode in the range of 10-30 mm, an internal reaction chamber pressure in the range of 100-150 mT, and a power supply of 200-500 W.

8. The method according to claim 7 , wherein the second process comprises supplying Cl 2 at a flow rate in the range of 80-150 sccm, HBr at a flow rate in the range of 0-50 sccm, and O 2 at a flow rate in the range of 0-20 sccm.

9. The method according to claim 1 , wherein forming the device isolation layer, forming the gate insulating layer and the gate electrode, depositing the triple layer, and forming the spacers are carried out within a capacitive coupled plasma (CCP) apparatus.

10. The method according to claim 1 , wherein forming the spacers further exposes the bottom oxide layer on an uppermost surface of the gate electrode.

11. The method according to claim 10 , further comprising forming a dielectric layer on the exposed bottom oxide layer.

12. The method according to claim 11 , wherein the dielectric layer comprises a nitride etch stop layer, a boron and/or phosphorous doped silicon oxide layer, and a undoped oxide layer, and/or a TEOS-based oxide layer.

13. The method according to claim 1 , further comprising etching the exposed bottom oxide layer to form an exposed active region.

14. The method according to claim 13 , further comprising ion implantation and silicide forming process to form source and drain terminals in the exposed active region.

15. A semiconductor substrate, comprising:

a semiconductor substrate;

a device isolation layer in a trench in the substrate, the device isolation layer comprising an oxide layer that fills the trench;

a gate insulating layer on the semiconductor substrate;

a gate electrode on the gate insulating layer; and

a spacer on a side of the gate electrode and a side of the gate insulating layer, the spacer including a triple layer having a bottom oxide layer on the device isolation layer and at least a top surface and sidewalls of the gate electrode and, a nitride layer, and a top oxide layer; and

a bulk dielectric layer directly on an exposed surface of the bottom oxide layer.

16. The semiconductor device according to claim 15 , wherein the bottom oxide layer contacts the gate electrode in a region where no gate insulating layer is formed.

17. The semiconductor device according to claim 15 , wherein the top oxide layer, the bottom oxide layer, and the device isolation layer comprise a same material.

18. The semiconductor device according to claim 15 , wherein the top oxide layer and the bottom oxide layer comprise a same material, and the oxide layer of the device isolation layer comprises a material different from that of the top oxide layer and the bottom oxide layer.

19. The semiconductor device according to claim 15 , wherein the top oxide layer and the bottom oxide layer comprise different materials, and the oxide layer of the device isolation layer comprises a same material as one of the top oxide layer and the bottom oxide layer.

20. The semiconductor device according to claim 15 , wherein the top oxide layer, the bottom oxide layer, and the device isolation layer comprise different materials from one another.