IP Library Granted Patent US 7,932,901
Granted Patent B2
US 7,932,901 · App. 11/880,699 · Granted Apr 26, 2011

Timing generating circuit, display apparatus, and portable terminal

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Quick Facts
Patent No.
US 7,932,901
App. No.
11/880,699
Granted
Apr 26, 2011
Kind
B2
Abstract

A timing generating circuit with low power consumption and a small layout area, a display apparatus including the timing generating circuit as one peripheral driving circuit, and a portable terminal including the display apparatus as a display output section are provided. In the timing generating circuit, which is formed on an insulating substrate and generates output pulses SRFF1out to SRFFnout having different frequencies based on a master clock MCK, a clock generating circuit ( 11 ) generates an operating clock having a lower frequency than the master clock MCK frequency. Then, a counter section ( 12 ) operates based on this operating clock and successively outputs shifted pulses S/R1out to S/Rmount from shift registers ( 121 - 1 ) to ( 121 -m). An output pulse generating section ( 13 ) generates output pulses SF1out to SFnout based on combinations of the shifted pulses S/R1out to S/Rmount.

Claims (21)

1. A method of generating a timing signal comprising:

providing an operating clock based on an input master clock, the operating clock having a lower frequency than the master clock frequency; generating multiple timing signals having different frequencies based on the operating clock; and

providing a counter section having multiple cascaded shift registers, the counter section performing count operations in synchronism with the operating clock; and providing a signal generating section that generates multiple timing signals according to combinations of shifted pulses output from the multiple shift registers.

2. The method of generating a timing signal according to claim 1 wherein the counter section performs the count operations in response to start pulses generated in a predetermined period.

3. A method of driving a display apparatus comprising:

providing a display section having a matrix of pixels substrate; and

providing a timing generating circuit and

generating circuit generating multiple timing signals having different frequencies required for driving the display section in synchronism with a master clock,

generating an operating clock based on the master clock, the operating clock having a lower frequency than the master clock frequency;

generating multiple timing signals based on the operating clock; and

providing a counter section in which multiple shift registers are cascaded, the counter section performing count operations in synchronism with the operating clock generated by the clock generating means; and

providing a signal generating section that generates the multiple timing signals according to combinations of shifted pulses output from the multiple shift registers.

4. The method of driving a display apparatus according to claim 3 , wherein the counter section performs the count operations in response to start pulses generated in a predetermined period.

5. The method of driving a display apparatus according to claim 3 wherein the timing generating circuit is formed on a transparent insulating substrate using low-temperature poly-silicon or continuous grain silicon.

6. A method for generating a display signal for a portable terminal comprising a display screen component including:

providing a display section having a matrix of pixels arranged on a transparent insulating substrate; and

generating multiple timing signals having different frequencies required for driving the display section in synchronism with a master clock,

generating an operating clock having a lower frequency than the master clock frequency based on the master clock;

generating the multiple timing signals based on the operating clock; and

providing a counter section in which multiple shift registers are cascaded, the counter section performing count operations in synchronism with the operating clock; and

generating multiple timing signals according to combinations of shifted pulses output from the multiple shift registers.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 8, 2013
From: SONY CORPORATION
To: JAPAN DISPLAY WEST INC.
Reel/Frame 031377/0850 →