A cache system is provided which includes a cache memory and a cache refill mechanism which allocates one or more of a set of cache partitions in the cache memory to an item in dependence on the address of the item in main memory. This is achieved in one of the described embodiments by including with the address of an item a set of partition selector bits which allow a partition mask to be generated to identify into which cache partition the item may be loaded.
1. A method of decreasing memory access latency in a system for processing items held in memory, the method comprising:
providing a cache memory having a set of cache partitions, each cache partition comprising a plurality of addressable storage locations for holding the items fetched from said memory for use by a processor;
loading an item fetched from said memory into one of the cache partitions in accordance with a partition indicator for the item, wherein the partition indicator identifies into which cache partition the item may be loaded; and
when the processor executes at least two processes simultaneously, altering the number of cache partitions when the processor switches from executing a process to executing another process.
2. The method of claim 1 , wherein the item is a data item.
3. The method of claim 1 , wherein the item is an instruction.
4. The method of claim 1 , wherein the memory is a main memory.
5. The method of claim 1 , wherein a number of the plurality of addressable storage locations in each cache partition is alterable.
6. The method of claim 1 , wherein each address in the memory comprises a page number and a line-in-page number and wherein a plurality of processes are held in the memory, each process including one or more sequences of instructions held at addresses in the memory with a common page number.
7. The method of claim 6 , wherein a cache partition from the set of cache partitions is allocated to a process by associating the cache partition with page numbers of the process in the memory.
8. The method of claim 7 , wherein the association of cache partitions with the page numbers is alterable while the process using the page numbers is being run by the processor.