Interface circuit
View Patent ↗An interface circuit is provided for use in a semiconductor device which transmits and receives a signal to and from the outside. The interface circuit includes a signal input/output terminal for receiving a signal from the outside in a signal input mode and a signal from the semiconductor device in a signal output mode, an input buffer gate circuit having an input terminal connected to the signal input/output terminal and for outputting a signal received at the input terminal to the semiconductor device, and an input level control circuit for fixing a potential level at the input terminal of the input buffer gate circuit to a predetermined level in a signal no-supply mode and removing the fixation of the potential level in the signal output mode and in the signal input mode.
1. An interface circuit for use in a semiconductor device having a signal output mode in which a signal is supplied to the outside, a signal input mode in which a signal is received from the outside, and a signal no-supply mode in which a signal is not supplied from the outside and a signal is not supplied to the outside, the circuit comprising:
a signal input/output terminal for receiving a signal from the outside in the signal input mode and a signal from the semiconductor device in the signal output mode;
an input buffer gate circuit having an input terminal connected to the signal input/output terminal and for outputting a signal received at the input terminal to the semiconductor device;
an output buffer gate circuit having an input terminal and an output terminal, the output terminal being connected to the signal input/output terminal, and having a signal output state in which a signal received at the input terminal is output, and a high-impedance state in which, even when a signal is received at the input terminal, the signal is not output;
an output control circuit for causing the output buffer gate circuit to go to the signal output state in the signal output mode and in the signal no-supply mode, and the high-impedance state in the signal input mode,
a level control circuit for outputting a first level signal in the signal output mode and a second level signal in the signal no-supply mode; and
a logic circuit connected between the semiconductor device and the input terminal of the output buffer gate circuit and for outputting a signal having a predetermined potential level to the output buffer gate circuit when the first level signal is output from the level control circuit and a signal from the semiconductor device to the output buffer gate circuit when the second level signal is output from the level control circuit.
2. The interface circuit of claim 1 , further comprising:
a resistance circuit having an ON state in which a potential level of the signal input/output terminal is pulled up or down and an OFF state in which the potential level of the signal input/output terminal is not pulled up or down; and
a resistance control circuit for causing the resistance circuit to go to the ON state in the signal no-supply mode and the OFF state in the signal output mode and in the signal input mode.
3. The interface circuit of claim 2 , wherein timing with which the resistance control circuit causes the resistance circuit to go to the ON state or the OFF state can be changed.
4. The interface circuit of claim 2 , wherein timing with which the resistance control circuit causes the resistance circuit to go to the ON state or the OFF state is set, depending on an external device connected to the interface circuit.
5. The interface circuit of claim 1 , wherein timing with the output control circuit causes the output buffer gate circuit to go to the signal output state or the high-impedance state and timing with which the level control circuit outputs the first level signal or the second level signal can each be changed.
6. The interface circuit of claim 1 , wherein timing with the output control circuit causes the output buffer gate circuit to go to the signal output state or the high-impedance state and timing with which the level control circuit outputs the first level signal or the second level signal are each set, depending on an external device connected to the interface circuit.
7. The interface circuit of claim 1 , further comprising:
a resistance circuit having an ON state in which a potential level of the signal input/output terminal is pulled up or down and an OFF state in which the potential level of the signal input/output terminal is not pulled up or down; and
a resistance control circuit for causing the resistance circuit to go to the ON state in the signal no-supply mode and the OFF state in the signal output mode, and detects a potential level at the input terminal of the input buffer gate circuit and, depending on a result of the detection of the potential level, causing the resistance circuit to go to the OFF state in the signal input mode.
8. The interface circuit of claim 7 , wherein of timing with which the resistance control circuit causes the resistance circuit to go to the ON state or the OFF state, timing other than the timing based on the result of the detection of the potential level can be changed.
9. The interface circuit of claim 7 , wherein of timing with which the resistance control circuit causes the resistance circuit to go to the ON state or the OFF state, timing other than the timing based on the result of the detection of the potential level is set, depending on an external device connected to the interface circuit.
10. An interface circuit for use in a semiconductor device having a signal output mode in which a signal is supplied to the outside, a signal input mode in which a signal is received from the outside, and a signal no-supply mode in which a signal is not supplied from the outside and a signal is not supplied to the outside, the circuit comprising:
a signal input/output terminal for receiving a signal from the outside in the signal input mode and a signal from the semiconductor device in the signal output mode;
an input buffer gate circuit having an input terminal connected to the signal input/output terminal and for outputting a signal received at the input terminal to the semiconductor device;
an output level control circuit for fixing a potential level at the output terminal of the input buffer gate circuit to a predetermined level in the signal no-supply mode and removing the fixation of the potential level in the signal input mode;
an output buffer gate circuit having an input terminal and an output terminal, the output terminal being connected to the signal input/output terminal, and having a signal output state in which a signal received at the input terminal is output, and a high-impedance state in which, even when a signal is received at the input terminal, the signal is not output;
an output control circuit for causing the output buffer gate circuit to go to the signal output state in the signal output mode and in the signal no-supply mode, and the high-impedance state in the signal input mode,
a level control circuit for outputting a first level signal in the signal output mode and a second level signal in the signal no-supply mode; and
a logic circuit connected between the semiconductor device and the input terminal of the output buffer gate circuit and for outputting a signal having a predetermined potential level to the output buffer gate circuit when the first level signal is output from the level control circuit and a signal from the semiconductor device to the output buffer gate circuit when the second level signal is output from the level control circuit.
11. The interface circuit of claim 10 , wherein timing with which the level control circuit outputs the first level signal or the second level signal can be changed.
12. The interface circuit of claim 10 , wherein timing with which the level control circuit outputs the first level signal or the second level signal is set, depending on an external device connected to the interface circuit.