Semiconductor device and method for manufacturing the same
A semiconductor device includes a first MIS transistor and a second MIS transistor. The first MIS transistor includes: a first gate insulating film formed on a first active region of a substrate; and a first gate electrode formed on the first gate insulating film. The second MIS transistor includes: a second gate insulating film formed on a second active region of the substrate and having a dielectric constant lower than the first gate insulating film; and a second gate electrode formed on the second gate insulating film. Insulting sidewall spacers having the same structure are formed on respective side faces of the first gate electrode and the second gate electrode.
1 . A semiconductor device, comprising a first MIS transistor and a second MIS transistor,
wherein the first MIS transistor includes:
a first gate insulating film formed on a first active region of a substrate; and
a first gate electrode formed on the first gate insulating film,
the second MIS transistor includes:
a second gate insulating film formed on a second active region of the substrate and having a dielectric constant lower than the first gate insulating film; and
a second gate electrode formed on the second gate insulating film, and
insulting sidewall spacers having the same structure are formed on respective side faces of the first gate electrode and the second gate electrode.
2 . The semiconductor device of claim 1 ,
wherein the first gate insulating film has a film thickness equal to or smaller than the second gate insulating film.
3 . The semiconductor device of claim 1 ,
wherein the first MIS transistor and the second MIS transistor have the same conductivity type, and
an operation voltage of the first MIS transistor is lower than an operation voltage of the second MIS transistor.
4 . The semiconductor device of claim 1 ,
wherein the first gate insulating film has a film thickness larger than the second gate insulating film.
5 . The semiconductor device of claim 1 ,
wherein the first MIS transistor is an N-type MIS transistor, and
the second MIS transistor is a P-type MIS transistor.
6 . The semiconductor device of claim 1 ,
wherein the first MIS transistor and the second MIS transistor have the same conductivity type,
an operation voltage of the first MIS transistor is equal to an operation voltage of the second MIS transistor, and
a threshold voltage of the first MIS transistor is higher than a threshold voltage of the second MIS transistor.
7 . The semiconductor device of claim 1 ,
wherein the first gate insulating film includes a high dielectric insulating film.
8 . The semiconductor device of claim 7 ,
wherein a SiN film is formed on the high dielectric insulating film.
9 . The semiconductor device of claim 7 ,
wherein the high dielectric insulating film includes a nitrided upper part.
10 . The semiconductor device of claim 7 ,
wherein a buffer insulating film is formed below the high dielectric insulating film.
11 . The semiconductor device of claim 1 ,
wherein the second gate insulating film is a SiO 2 film or a SiON film.
12 . The semiconductor device of claim 1 ,
wherein the first gate electrode is a fully silicided electrode, and
the second gate electrode is a fully silicided electrode or includes a polysilicon electrode.
13 . The semiconductor device of claim 1 ,
wherein the first gate electrode and the second gate electrode are metal gate electrodes.
14 . The semiconductor device of claim 1 ,
wherein the first gate electrode is a metal gate electrode, and
the second gate electrode includes a polysilicon electrode in contact with the second gate insulating film.
15 . The semiconductor device of claim 1 ,
wherein the first gate electrode includes a metal gate electrode in contact with the first gate insulating film, and
the second gate electrode includes a polysilicon electrode in contact with the second gate insulating film.
16 . The semiconductor device of claim 15 , further comprising a third MIS transistor,
wherein the third MIS transistor includes:
a third gate insulating film formed on a third active region of the substrate and formed of the same insulating film as the first gate insulating film; and
a third gate electrode formed on the third gate insulating film,
the third gate electrode includes another metal gate electrode in contact with the third gate insulating film, and
insulating sidewall spacers having the same structure as the said insulating sidewall spacers are formed on the respective side faces of the third gate electrode.
17 . The semiconductor device of claim 1 , further comprising a third MIS transistor,
wherein the third MIS transistor includes:
a third gate insulating film formed on a third active region of the substrate and having a dielectric constant lower than the first gate insulating film; and
a third gate electrode formed on the third gate insulating film, and
insulating sidewall spacers having the same structure as the said insulating sidewall spacers are formed on the respective side faces of the third gate electrode.
18 . A method for manufacturing a semiconductor device including a first MIS transistor including a first gate insulating film and a first gate electrode and a second MIS transistor including a second gate insulating film and a second gate electrode, the method comprising the steps of:
(a) forming the first gate insulating film on a first active region of a substrate;
(b) forming the second gate insulating film, which has a dielectric constant lower than the first gate insulating film, on a second active region of the substrate;
(c) forming the first gate electrode on the first gate insulating film;
(d) forming the second gate electrode on the second gate insulating film; and
(e) forming insulating sidewall spacers having the same structure on respective side faces of the first gate electrode and the second gate electrode.
19 . The method of claim 18 ,
wherein the first gate insulating film has a film thickness equal to or smaller than the second gate insulating film.
20 . The method of claim 18 ,
wherein the first MIS transistor and the second MIS transistor have the same conductivity type, and
an operation voltage of the first MIS transistor is lower than an operation voltage of the second MIS transistor.
21 . The method of claim 18 ,
wherein the first gate insulating film has a film thickness larger than the second gate insulating film.
22 . The method of claim 18 ,
wherein the first MIS transistor is an N-type MIS transistor, and
the second MIS transistor is a P-type MIS transistor.
23 . The method of claim 18 ,
wherein the first MIS transistor and the second MIS transistor have the same conductivity type,
an operation voltage of the first MIS transistor is equal to an operation voltage of the second MIS transistor; and
a threshold voltage of the first MIS transistor is higher than a threshold voltage of the second MIS transistor.
24 . The method of claim 18 ,
wherein the step (a) includes a step of forming, after forming a high dielectric insulating film on the first active region, an SiN film on the high dielectric insulating film, and
the step (b) includes a step of forming the second gate insulating film on the second active region by oxidizing the substrate with the use of the SiN film as a mask after the step (a).
25 . The method of claim 24 , further comprising the step of:
removing the SiN film after the step (b) and before the step (c).
26 . The method of claim 18 ,
wherein the step (a) includes a step of forming, after forming a high dielectric insulating film on the first active region, a nitride layer by nitriding an upper part of the high dielectric insulating film, and
the step (b) includes a step of forming the second gate insulating film on the second active region by oxidizing the substrate with the use of the nitride layer as a mask after the step (a).
27 . The method of claim 26 , further comprising the step of:
removing the nitride layer after the step (b) and before the step (c).
28 . The method of claim 24 ,
wherein the step (a) includes a step of forming, before forming the high dielectric insulating film, a buffer insulating film on the first active region.
29 . The method of claim 18 ,
wherein the second gate insulating film is a SiO 2 film or a SiON film.
30 . The method of claim 18 ,
wherein the first gate electrode and the second gate electrode are made of polysilicon,
the method comprising the step of:
fully siliciding at least the first gate electrode after the step (c).
31 . The method of claim 18 ,
wherein the first gate electrode and the second gate electrode are metal gate electrodes.
32 . The method of claim 18 ,
wherein in the step (c), a dummy gate electrode is formed in place of the first gate electrode,
the method further comprising the steps of:
(f) removing, after the step (e), the dummy gate electrode and forming a metal gate electrode as the first gate electrode in a recessed portion formed by the removal.
33 . The method of claim 32 ,
wherein the second gate electrode is formed of a silicon-containing film,
the method further comprising the step of:
forming a protection film covering the dummy gate electrode and siliciding a surface portion of the second gate electrode with the use of the protection film as a mask between the step (e) and the step (f),
wherein in the step (f), the protection film is removed together with the dummy gate electrode.
34 . The method of claim 18 ,
wherein in the step (c) and the step (d): a metal film is formed on the first gate insulating film; a polysilicon film is formed on the metal film and the second gate insulating film; and then, patterning is performed on the metal film and the polysilicon film on the first gate insulating film and the polysilicon film on the second gate insulating film to form the first gate electrode and the second gate electrode.
35 . The method of claim 18 ,
wherein the semiconductor device further includes a third MIS transistor including a third gate insulating film and a third gate electrode,
in the step (a), the third gate insulating film, which is made of the same insulating film as the first gate insulating film, is formed on a third active region of the substrate,
in the step (c) and the step (d): a first metal film is formed on the first gate insulating film while a second metal film is formed on the third gate insulating film; a polysilicon film is formed on the first metal film, the second metal film, and the second gate insulating film; and then, patterning is performed on the first metal film and the polysilicon film on the first gate insulating film, the polysilicon film on the second gate insulating film, and the second metal film and the polysilicon film on the third gate insulating film to form the first gate electrode, the second gate electrode, and the third gate electrode, respectively, and
in the step (e), insulating sidewall spacers having the same structure as the said insulating sidewall spacers are formed on the respective side faces of the third gate electrode.
36 . The method of claim 18 ,
wherein the semiconductor device further includes a third MIS transistor including a third gate insulating film and a third gate electrode,
the method further comprising the steps of:
(g) forming the third gate insulating film, which has a dielectric constant lower than the first gate insulating film, on a third active region of the substrate before the step (c) and the step (d); and
(h) forming the third gate electrode on the third gate insulating film between the step (g) and the step (e),
wherein in the step (e), insulating sidewall spacers having the same structure as the said insulating sidewall spacers are formed on the respective side faces of the third gate electrode.