Self-modifying FPGA for anti-tamper applications
View Patent ↗A self-modifying FPGA system includes an FPGA and a configuration memory device coupled to the FPGA for providing the FPGA with configuration information. The configuration memory device is programmed with configuration data and dormant data. The FPGA system is also provided with a configuration assist circuit coupled to the FPGA and the configuration memory device for controlling loading of configuration information from the configuration memory device to the FPGA. A tamper detection system provides a tamper signal to the FPGA, wherein when a tamper signal is received by the FPGA the configuration data is replaced with the dormant data.
1. A self-modifying FPGA system, comprising:
an FPGA;
a configuration memory device coupled to the FPGA for providing the FPGA with configuration information, the configuration memory device programmed with configuration data and dormant data;
configuration assist circuit coupled to the FPGA and the configuration memory device for controlling loading of configuration information from the configuration memory device to the FPGA;
a tamper detection system providing a tamper indication signal to the FPGA, wherein when a tamper indication signal is received by the FPGA the configuration data is replaced with the dormant data and
wherein the FPGA includes a configuration block in communication with a configuration assist circuitry to assist in rewriting configuration data from the configuration memory device.
2. The FPGA system according to claim 1 , wherein the FPGA is a SRAM based FPGA.
3. The FPGA system according to claim 2 , wherein the configuration memory device is a PROM.
4. The FPGA system according to claim 3 , wherein the PROM is a FLASH based PROM.
5. The FPGA system according to claim 1 , wherein the configuration memory device is a PROM.
6. The FPGA system according to claim 5 , wherein the PROM is a FLASH based PROM.
7. The FPGA system according to claim 1 , wherein the configuration assist circuitry includes means for initiating a reload of the dormant data from the configuration memory device to the FPGA amounting to reconfiguration of the FPGA upon receipt of a tamper indication signal.
8. The FPGA system according to claim 1 , wherein the configuration memory device is further provided with null data.
9. The FPGA system according to claim 1 , wherein the configuration memory device is further provided with a first set of dormant data and a second set of dormant data.
10. A self-modifying FPGA system, comprising:
an FPGA;
a configuration memory device coupled to the FPGA for providing the FPGA with configuration information the configuration memory device programmed with configuration data and dormant data;
configuration assist circuit coupled to the FPGA and the configuration memory device for controlling loading of configuration information from the configuration memory device to the FPGA;
a tamper detection system providing a tamper indication signal to the FPGA, wherein when a tamper indication signal is received by the FPGA the configuration data is replaced with the dormant data; and
wherein the configuration data is located beginning at a zero address of the configuration memory device and the FPGA system includes means for transferring the dormant data to the zero address upon the initiation of tamper indication signal.
11. The FPGA system according to claim 10 , wherein the means for transferring includes means for clearing or over writing the configuration data with null data, reading the dormant data and writing the dormant data to the zero address.
12. The FPGA system according to claim 10 , wherein the FPGA is a SRAM based FPGA.
13. The FPGA system according to claim 12 , wherein the configuration memory device is a PROM.
14. The FPGA system according to claim 13 , wherein the PROM is a FLASH based PROM.
15. The FPGA system according to claim 10 , wherein the configuration memory device is a PROM.
16. The FPGA system according to claim 15 , wherein the PROM is a FLASH based PROM.
17. The FPGA system according to claim 10 , wherein the FPGA includes a configuration block in communication with a configuration assist circuitry to assist in rewriting configuration data from the configuration memory device.
18. The FPGA system according to claim 17 , wherein the configuration assist circuitry includes means for initiating a reload of the dormant data from the configuration memory device to the FPGA amounting to reconfiguration of the FPGA upon receipt of a tamper indication signal.
19. The FPGA system according to claim 10 , wherein the configuration memory device is further provided with null data.
20. The FPGA system according to claim 10 , wherein the configuration memory device is further provided with a first set of dormant data and a second set of dormant data.