IP Library Granted Patent US 7,786,548
Granted Patent B2
US 7,786,548 · App. 11/883,481 · Granted Aug 31, 2010

Electric element, memory device, and semiconductor integrated circuit

Assignee: Panasonic Corporation
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Quick Facts
Patent No.
US 7,786,548
App. No.
11/883,481
Granted
Aug 31, 2010
Kind
B2
Abstract

An electric element includes a first electrode ( 1 ), a second electrode ( 3 ), and a variable-resistance film ( 2 ) connected between the first electrode ( 1 ) and the second electrode ( 3 ). The variable-resistance film ( 2 ) contains Fe (iron) and O (oxygen) as constituent elements. The content of oxygen in the variable-resistance film ( 2 ) is modulated along the film thickness direction.

Claims (51)

1. An electric element, comprising:

a first electrode;

a second electrode; and

a variable-resistance film connected between the first electrode and the second electrode,

wherein the variable-resistance film contains Fe (iron) and O (oxygen) as constituent elements, and the content of oxygen is modulated along a film thickness direction.

2. The electric element of claim 1 , wherein:

the variable-resistance film includes a plurality of reference layers deposited in succession along the film thickness direction; and

the oxygen content in each of the plurality of reference layers is different from those of neighboring reference layers.

3. The electric element of claim 1 , wherein:

the variable-resistance film includes a plurality of periodic unit layers deposited in succession along the film thickness direction;

each of the plurality of periodic unit layers includes a plurality of reference layers deposited in succession along the film thickness direction; and

the oxygen content in each of the plurality of reference layers is different from those of neighboring reference layers.

4. The electric element of claim 3 , wherein the plurality of reference layers include a first reference layer having a first oxygen content and a second reference layer having a second oxygen content and deposited on the first reference layer.

5. The electric element of claim 3 , wherein the oxygen content in each of the plurality of reference layers is different from those of the other reference layers included in the same periodic unit layer.

6. The electric element of claim 3 , wherein the thickness of the periodic unit layer is 50 nm or less.

7. The electric element of claim 1 , wherein:

the variable-resistance film includes a plurality of periodic unit layers deposited in succession along the film thickness direction; and

each of the plurality of periodic unit layers has an oxygen content gradually changing along the film thickness direction.

8. The electric element of claim 7 , wherein the thickness of the periodic unit layer is 50 nm or less.

9. The electric element of claim 1 , wherein the thickness of the variable-resistance film is 200 nm or less.

10. The electric element of claim 1 , wherein at least one of the first electrode and the second electrode is formed using any of Ag, Au, Pt, Ru, RuO 2 , Ir, and IrO 2 .

11. The electric element of claim 1 , wherein the electric element stores 1-bit or multi-bit information by applying a predetermined electric pulse between the first electrode and the second electrode such that the resistance value is changed.

12. The electric element of claim 1 , wherein 1-bit or multi-bit information is read from the electric element by applying a predetermined voltage between the first electrode and the second electrode such that an electric current flows according to the resistance value of the electric element.

13. A memory device, comprising:

a plurality of word lines;

a plurality of bit lines;

a plurality of plate lines corresponding to the plurality of bit lines on a one-to-one basis;

a plurality of transistors;

a plurality of electric elements corresponding to the plurality of transistors on a one-to-one basis;

a word line driver for driving the plurality of word lines; and

a bit line/plate line driver for driving the plurality of bit lines and the plurality of plate lines,

wherein each of the plurality of transistors and an electric element corresponding to the transistor are connected in series between any one of the plurality of bit lines and a plate line corresponding to the bit line,

each of the plurality of transistors is connected between a bit line corresponding to the transistor and an electric element corresponding to the transistor, a gate of the transistor being connected to any one of the plurality of word lines,

each of the plurality of electric elements includes a first electrode connected to a transistor corresponding to the electric element, a second electrode connected to a plate line corresponding to the electric element, and a variable-resistance film connected between the first electrode and the second electrode, and

the variable-resistance film contains Fe (iron) and O (oxygen) as constituent elements, and the content of oxygen is modulated along the film thickness direction.

14. The memory device of claim 13 , wherein in order to store information in any one of the plurality of electric elements,

the word line driver applies an activation voltage to one of the plurality of word lines connected to the electric element in which the information is to be stored; and

the bit line/plate line driver applies a first electric pulse to one of the plurality of bit lines connected to the electric element in which the information is to be stored and applies a second electric pulse to a plate line corresponding to the bit line.

15. The memory device of claim 13 , wherein in order to reproduce information stored in any one of the plurality of electric elements,

the word line driver applies an activation voltage to one of the plurality of word lines connected to the electric element from which the information is to be read; and

the bit line/plate line driver applies a first reproduction voltage to one of the plurality of bit lines connected to the electric element from which the information is to be read and applies a second reproduction voltage to a plate line corresponding to the bit line.

16. A semiconductor integrated circuit, comprising:

the memory device of claim 13 ; and

a logic circuit which has a memorization mode and a reproduction mode,

wherein in the memorization mode, the logic circuit stores bit data in the memory device, and

in the reproduction mode, the logic circuit reads bit data stored in the memory device.

17. A semiconductor integrated circuit, comprising:

the memory device of claim 13 ; and

a processor which has a program execution mode and a program rewrite mode,

wherein in the program execution mode, the processor operates according to a program stored in the memory device, and

in the program rewrite mode, the processor rewrites a program stored in the memory device to another new program received from outside.

Assignments (2)
CHANGE OF NAME Recorded Nov 20, 2008
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 021897/0534 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2008
From: OSANO, KOICHI; MURAOKA, SHUNSAKU; MITANI, SATORU; NAGO, KUMIO
To: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Reel/Frame 021039/0583 →
Priority Claims (1)
JP 2005-369090 · Dec 22, 2005 · national
Continuity (1)
Related Publication 20080111245A1 · May 15, 2008