Memory device and semiconductor integrated circuit
View Patent ↗First electrode layer includes a plurality of first electrode lines (W 1 , W 2 ) extending parallel to each other. State-variable layer lying on the first electrode layer includes a plurality of state-variable portions ( 60 - 11, 60 - 12, 60 - 21, 60 - 22 ) which exhibits a diode characteristic and a variable-resistance characteristic. Second electrode layer lying on the state-variable layer includes a plurality of second electrode lines (B 1 , B 2 ) extending parallel to each other. The plurality of first electrode lines and the plurality of second electrode lines are crossing each other when seen in a layer-stacking direction with the state-variable layer interposed therebetween. State-variable portion ( 60 - 11 ) is provided at an intersection of the first electrode line (W 1 ) and the second electrode line (B 1 ) between the first electrode line and the second electrode line.
1. A memory device, comprising:
a first electrode layer including a plurality of first electrode lines extending parallel to each other;
a state-variable layer lying on the first electrode layer, the state-variable layer including a plurality of state-variable portions, the plurality of state-variable portions being a plurality of state-variable portions formed of a state-variable material which exhibits a diode characteristic and a variable-resistance characteristic; and
a second electrode layer lying on the state-variable layer, the second electrode layer including a plurality of second electrode lines extending parallel to each other,
wherein the plurality of first electrode lines and the plurality of second electrode lines are crossing each other when seen in a layer-stacking direction with the state-variable layer interposed therebetween,
each of the plurality of state-variable portions is provided at an intersection of any one of the plurality of first electrode lines and any one of the plurality of second electrode lines when seen in the layer-stacking direction between the first electrode line and the second electrode line, each state-variable portion exhibiting a diode characteristic such that a forward direction is the direction extending from one of the first electrode line and the second electrode line to the other while a reverse direction is opposite to the forward direction, each state-variable portion exhibiting a variable-resistance characteristic such that a resistance value of the state-variable portion in the forward direction increases/decreases according to a predetermined pulse voltage applied between the first electrode line and the second electrode line.
2. The memory device of claim 1 , further comprising a plurality of first electrodes and a plurality of second electrodes, the first and second electrodes corresponding to the plurality of state-variable portions,
wherein each of the plurality of first electrodes intervenes between a state-variable portion corresponding to the first electrode and a first electrode line corresponding to the state-variable portion,
each of the plurality of second electrodes intervenes between a state-variable portion corresponding to the second electrode and a second electrode line corresponding to the state-variable portion, and
each of the plurality of state-variable portions exhibits a diode characteristic such that a forward direction is the direction extending from one of the corresponding first and second electrodes to the other electrode while a reverse direction is opposite to the forward direction, and a variable-resistance characteristic such that a resistance value of the state-variable portion in the forward direction increases/decreases according to a predetermined pulse voltage applied between the first electrode and the second electrode.
3. The memory device of claim 1 , wherein the work function of each of the plurality of first electrode lines is different from the work function of each of the plurality of second electrode lines.
4. The memory device of claim 1 , wherein the crystallinity of the state-variable material in each of the plurality of state-variable portions is nonuniform.
5. The memory device of claim 1 , further comprising:
a first electrode line driver for applying a predetermined voltage to the plurality of first electrode lines; and
a second electrode line driver for applying a predetermined voltage to the plurality of second electrode lines.
6. The memory device of claim 1 , wherein the state-variable material is a metal oxide having a spinel structure.
7. The memory device of claim 1 , wherein the state-variable material is a ferroelectric oxide containing a metal added thereto.
8. The memory device of claim 1 , wherein the state-variable material is a metal oxide having a perovskite structure.
9. The memory device of claim 1 , wherein the state-variable material does not contain an alkali metal or alkaline-earth metal.
10. The memory device of claim 2 , wherein the work function of each of the plurality of first electrodes is different from the work function of each of the plurality of second electrodes.
11. A memory device, comprising:
a first electrode layer including a plurality of first electrode lines extending parallel to each other;
a state-variable layer lying on the first electrode layer, the state-variable layer being formed of a state-variable material which exhibits a diode characteristic and a variable-resistance characteristic; and
a second electrode layer lying on the state-variable layer, the second electrode layer including a plurality of second electrode lines extending parallel to each other,
wherein the plurality of first electrode lines and the plurality of second electrode lines are crossing each other when seen in a layer-stacking direction with the state-variable layer interposed therebetween,
in the state-variable layer, a state-variable portion which is a variable region interposed between any one of the plurality of first electrode lines and any one of the plurality of second electrode lines exhibits a diode characteristic such that a forward direction is the direction extending from one of the first electrode line and the second electrode line to the other while a reverse direction is opposite to the forward direction and a variable-resistance characteristic such that a resistance value of the state-variable portion in the forward direction increases/decreases according to a predetermined pulse voltage applied between the first electrode line and the second electrode line.
12. The memory device of claim 11 , wherein the crystallinity of the state-variable material in the state-variable layer is nonuniform.
13. The memory device of claim 11 , wherein the work function of each of the plurality of first electrode lines is different from the work function of each of the plurality of second electrode lines.
14. The memory device of claim 11 , further comprising:
a first electrode line driver for applying a predetermined voltage to the plurality of first electrode lines; and
a second electrode line driver for applying a predetermined voltage to the plurality of second electrode lines.
15. The memory device of claim 11 , wherein the state-variable material is a metal oxide having a spinel structure.
16. The memory device of claim 11 , wherein the state-variable material is a ferroelectric oxide containing a metal added thereto.
17. The memory device of claim 11 , wherein the state-variable material is a metal oxide having a perovskite structure.
18. The memory device of claim 11 , wherein the state-variable material does not contain an alkali metal or alkaline-earth metal.
19. The memory device of claim 5 wherein, in order to store information in any one of the plurality of state-variable portions,
the first electrode line driver applies a first pulse voltage to one of the plurality of first electrode lines corresponding to the state-variable portion in which the information is to be stored, and
the second electrode line driver applies a second pulse voltage to one of the plurality of second electrode lines corresponding to the state-variable portion in which the information is to be stored.
20. The memory device of claim 5 wherein, in order to reproduce information stored in any one of the plurality of state-variable portions,
the first electrode line driver applies a reproduction voltage to one of the plurality of first electrode lines corresponding to the state-variable portion from which the information is to be read, and
the second electrode line driver applies the reproduction voltage to the plurality of second electrode lines except for one corresponding to the state-variable portion from which the information is to be read.
21. A semiconductor integrated circuit, comprising:
the memory device of claim 5 ; and
a logic circuit for performing a predetermined operation
wherein the logic circuit has a memorization mode and a processing mode such that the logic circuit in the memorization mode stores bit data in the memory device, and the logic circuit in the processing mode reads bit data stored in the memory device.
22. A semiconductor integrated circuit, comprising:
the memory device of claim 5 ; and
a processor having a program execution mode and a program rewrite mode,
wherein the processor in the program execution mode operates according to a program stored in the memory device, and the processor in the program rewrite mode replaces a program stored in the memory device with an externally-input new program.
23. The memory device of claim 7 , wherein the ferroelectric oxide has an ilmenite structure.
24. The memory device of claim 8 , wherein the metal oxide has at least one of a CMR characteristic and high-temperature superconductivity.
25. The memory device of claim 14 wherein, in order to store information in any one of the plurality of state-variable portions,
the first electrode line driver applies a first pulse voltage to one of the plurality of first electrode lines corresponding to the state-variable portion in which the information is to be stored, and
the second electrode line driver applies a second pulse voltage to one of the plurality of second electrode lines corresponding to the state-variable portion in which the information is to be stored.
26. The memory device of claim 14 wherein, in order to reproduce information stored in any one of the plurality of state-variable portions,
the first electrode line driver applies a reproduction voltage to one of the plurality of first electrode lines corresponding to the state-variable portion from which the information is to be read, and
the second electrode line driver applies the reproduction voltage to the plurality of second electrode lines except for one corresponding to the state-variable portion from which the information is to be read.
27. A semiconductor integrated circuit, comprising:
the memory device of claim 14 ; and
a logic circuit for performing a predetermined operation
wherein the logic circuit has a memorization mode and a processing mode such that the logic circuit in the memorization mode stores bit data in the memory device, and the logic circuit in the processing mode reads bit data stored in the memory device.
28. A semiconductor integrated circuit, comprising:
the memory device of claim 14 ; and
a processor having a program execution mode and a program rewrite mode,
wherein the processor in the program execution mode operates according to a program stored in the memory device, and the processor in the program rewrite mode replaces a program stored in the memory device with an externally-input new program.
29. The memory device of claim 16 , wherein the ferroelectric oxide has an ilmenite structure.
30. The memory device of claim 17 , wherein the metal oxide has at least one of a CMR characteristic and high-temperature superconductivity.