IP Library Granted Patent US 7,873,932
Granted Patent B2
US 7,873,932 · App. 11/885,831 · Granted Jan 18, 2011

Method for analyzing component mounting board

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Quick Facts
Patent No.
US 7,873,932
App. No.
11/885,831
Granted
Jan 18, 2011
Kind
B2
Abstract

A method for analyzing a component mounting board comprising a step (A) for forming a multilayer substrate shell model of a multilayer wiring board, a step (B) for forming a multilayer component shell model divided by element division lines based on the bonding position of a component to the surface of the multilayer wiring board, step (C) for redividing the mounting position of the component in the multilayer substrate shell model, and step (D) for forming an analysis model by bonding the neutral plane of the substrate and the neutral plane of the component through one of a beam element and a solid element, i.e. a bonding element equivalent to mounting conditions of the component, wherein precision of analysis is enhanced while reducing computation cost by performing calculation while imparting boundary conditions to the analysis model.

Claims (15)

1. A method for analyzing physical properties of a component mounting board, whereon a component is mounted to a surface of a multilayer wiring board, the method comprising:

generating electronic single layer models of layers of a multilayer wiring board which layers are internally divided into three-dimensional elements by a first set of element division lines, and including exclusive information about each such layer, on a basis of an external geometry of the multilayer wiring board and wiring patterns of the layers;

generating an electronic multilayer substrate shell model in which the single layer models of the layers are stacked in the geometry of the multilayer wiring board using thickness information for each of the layers of the multilayer wiring board;

generating an electronic multilayer component shell model based on a bonding position of a component to the surface of the multilayer wiring board divided into two-dimensional elements by a second set of element division lines;

electronically generating a mounting position of a component of a multilayer substrate shell model by redividing the three-dimensional elements defined by the first set of element division lines used in generating the multilayer component shell model;

forming an electronic analysis model of a mounting board with a component thereon, by connecting a neutral substrate plane computed from the redivided multilayer substrate shell model and a neutral component plane computed from the multilayer component shell model with a bonding element representing a component mounted on such a board; and

computing deformation of such a model mounting board by applying stress conditions to the analysis model.

2. The method for analyzing the component mounting board according to claim 1 , wherein forming the electronic analysis model by connecting the neutral substrate plane and the neutral component plane with a bonding element representing a component mounted on such board comprises:

computing the electronic analysis model by connecting a node of a resin bonding material area, excluding a node connected with one of the bonding element between the multilayer substrate shell model and the multilayer component shell model, with a bonding element having a mechanical strength equivalent to that of a resin bonding material of the resin bonding material area.

3. A method for analyzing physical properties of a component mounting board, whereon a component is mounted to a surface of a multilayer wiring board, the method comprising:

generating electronic single layer models of layers of a multilayer wiring board which layers are internally divided into three-dimensional elements by a first set of element division lines, and including exclusive information about each such layer, on a basis of an external geometry of the multilayer wiring board, wiring patterns of the layers and a position of a land to which the component is surface-mounted;

generating an electronic multilayer substrate shell model in which the single layer models of the layers are stacked in the geometry of the multilayer wiring board using thickness information of each of the layers of the multilayer wiring board;

generating an electronic multilayer component shell model divided into two-dimensional elements by a second set of element division lines based on a bonding position to the surface of the multilayer wiring board of the component;

forming an electronic analysis model of a mounting board with a component thereon, by connecting a neutral substrate plane computed from the multilayer substrate shell model and a neutral component plane computed from the multilayer component shell model with a bonding element representing a component mounted on such a board; and

computing deformation of such a model mounting board by applying stress conditions to the analysis model.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 10, 2014
From: PANASONIC CORPORATION (FORMERLY MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.)
To: GODO KAISHA IP BRIDGE 1
Reel/Frame 032209/0630 →
CHANGE OF NAME Recorded Nov 14, 2008
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 021835/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 7, 2008
From: KAKINO, MANABU; OKAZAKI, TORU; IWASE, TEPPEI; TAKADA, KAZUNORI; FUJIWARA, HIROAKI; KUROISHI, TOMOAKI
To: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Reel/Frame 020619/0097 →