Liquid crystal driver, liquid crystal display device, and liquid crystal driving method

1. A liquid crystal driver for driving a liquid crystal display panel which includes P source lines, P being a natural number, the driver comprising:

a gray level voltage generator for generating N gray level voltages which have different voltage values from one another, N being a natural number;

an operational amplifier for amplifying an input voltage;

P selectors corresponding to the P source lines;

P connection switching sections corresponding to the P selectors and disposed between the P selectors and the P source lines; and

a controller for controlling the P connection switching sections, wherein:

each of the P selectors receives pixel data indicative of a gray level to select one of the N gray level voltages generated by the gray level voltage generator which corresponds to the pixel data and outputs the selected gray level voltage,

each of the P connection switching sections has a voltage write mode and a voltage retention mode,

in the voltage write mode, each of the connection switching sections supplies an output of a corresponding one of the P selectors to the operational amplifier and supplies an output of the operational amplifier to a corresponding one of the P source lines,

in the voltage retention mode, each of the connection switching sections supplies an output of a corresponding one of the P selectors to a corresponding one of the P source lines, and

the controller is configured to:

set each of the P connection switching sections into the voltage write mode at least once;

for each of the P connection switching sections set into the voltage write mode, after passage of a first predetermined interval, shift said each of the P connection switching sections from the voltage write mode to the voltage retention mode; and

after all of the P connection switching sections have been set to the voltage write mode at least once and shifted to the voltage retention mode, maintain all of the P connection switching sections in the voltage retention mode until a second predetermined interval passes.

2. The liquid crystal driver of claim 1 , wherein the controller carries out the mode shift in each of the P connection switching sections more than once during the second predetermined interval.

3. The liquid crystal driver of claim 1 , further comprising a power controller, wherein

if any one of the P connection switching sections is in the voltage write mode, the power controller supplies power to the operational amplifier, and

if all of the P connection switching sections are in the voltage retention mode, the power controller interrupts supply of power to the operational amplifier.

4. The liquid crystal driver of claim 1 , wherein the gray level voltage generator includes:

a ladder resistor connected between a first reference node and a second reference node, the ladder resistor including N taps; and

N amplification operational amplifiers corresponding to the N taps of the ladder resistor,

wherein each of the N amplification operational amplifiers is connected between a corresponding one of the N taps and each of the P selectors.

5. The liquid crystal driver of claim 1 , wherein the gray level voltage generator includes:

a first ladder resistor connected between a first reference node and a second reference node, the first ladder resistor including N first taps;

a second ladder resistor connected between a third reference node and a fourth reference node, the second ladder resistor including N second taps; and

a ladder resistor connector for connecting, if all of the P connection switching sections are in the voltage retention mode, the N first taps of the first ladder resistor and the N second taps of the second ladder resistor on a one-to-one basis.

6. The liquid crystal driver of claim 5 , wherein the gray level voltage generator further includes a power controller, wherein

if any one of the P connection switching sections is in the voltage write mode, the power controller supplies power to the second ladder resistor, and

if all of the P connection switching sections are in the voltage retention mode, the power controller interrupts supply of the power to the second ladder resistor.

7. A liquid crystal display device, comprising:

the liquid crystal driver of claim 1 ;

a liquid crystal display panel including the P source lines, Q gate lines, Q being a natural number, and P×Q pixel cells; and

a gate driver for driving the Q gate lines,

wherein each of the P×Q pixel cells includes a switching element and a liquid crystal element.

8. The liquid crystal driver of claim 1 , wherein the P connection switching sections are sequentially set into the voltage write mode.

9. The liquid crystal driver of claim 8 , wherein more than one of the P connection switching sections are not simultaneously set into the voltage write mode.

10. The liquid crystal driver of claim 1 , wherein one operational amplifier as the operational amplifier is provide for all of the P selectors, and said one operation amplifier supplies the output to the P source lines.

11. A liquid crystal driver for driving a liquid crystal display panel which includes P source lines, P being a natural number, the driver comprising:

a gray level voltage generator for generating N gray level voltages which have different voltage values from one another, N being a natural number;

an operational amplifier for amplifying an input voltage;

P selectors corresponding to the P source lines;

P first switches corresponding to the P selectors;

P second switches corresponding to the P source lines;

P third switches corresponding to the P selectors; and

a controller for controlling the P first, second and third switches, wherein:

each of the P selectors receives pixel data indicative of a gray level to select one of the N gray level voltages generated by the gray level voltage generator which corresponds to the pixel data and outputs the selected gray level voltage,

each of the P first switches is connected between a corresponding one of the P selectors and the operational amplifier,

each of the P second switches is connected between a corresponding one of the P source lines and the operational amplifier,

each of the P third switches is connected between a corresponding one of the P selectors and a corresponding one of the P source lines, and

the controller is configured to during an operation interval:

turn each pair of the first and second P switches ON at least once;

for each pair of the first and second P switches turned ON, after passage of a predetermined interval, turn said each pair of the first and second P switches OFF and turn a corresponding one of the third P switches ON; and

after all of the third P switches have been turned ON, maintains all of the first and second P switches OFF and all of the third P switches ON until a predetermined timing.

12. The liquid crystal driver of claim 11 , wherein pairs of the first and second P switches are sequentially set into the voltage write mode.

13. The liquid crystal driver of claim 12 , wherein more than one pair of the first and second switches are not simultaneously set into the voltage write mode.

14. A method for driving a liquid crystal display panel which includes P source lines and corresponding P connection switching sections, P being a natural number, the method comprising the steps of:

(A) generating N gray level voltages which have different voltage values from one another, N being a natural number;

(B) receiving pixel data indicative of a gray level to select one of the N gray level voltages generated at step (A) which corresponds to the pixel data;

(C) amplifying the gray level voltage selected at step (B) to supply the amplified gray level voltage to the P source lines; and

(D) after step (C), supplying the gray level voltage selected at step (B) to the P source lines, wherein:

the steps (C) and (D) further includes, during an operation interval:

setting each of the P connection switching sections into a voltage write mode at least once to supply the amplified gray level voltage corresponding to said each of the P connection switching sections to be set into the voltage write mode;

for each of the P connection switching sections set into the voltage write mode, after passage of a first predetermined interval, shifting said each of the P connection switching sections from the voltage write mode to a voltage retention mode; and

after all of the P connection switching sections have been set to the voltage write mode at least once and shifted to the voltage retention mode, maintaining all of the P connection switching sections in the voltage retention mode until a second predetermined interval passes.

15. The method of claim 14 , wherein the P connection switching sections are sequentially set into the voltage write mode.

16. The method of claim 15 , wherein more than one of the P connection switching sections are not simultaneously set into the voltage write mode.