IP Library Granted Patent US 8,010,868
Granted Patent B2
US 8,010,868 · App. 11/889,152 · Granted Aug 30, 2011

Method for processing noise interference

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Quick Facts
Patent No.
US 8,010,868
App. No.
11/889,152
Granted
Aug 30, 2011
Kind
B2
Abstract

A method for processing noise interference in a serial AT Attachment (SATA) interface. The method includes the steps of detecting whether there is an error in CRC (Cyclic Redundancy Check) checksum or whether an R_ERR primitive (reception error primitive) is received, detecting whether a FIS (Frame Information Structure) is a data type if there is any error and returning back to error state detecting step if there is no any error, detecting whether the FIS is a ATAPI packet command CDB (Command Descriptor Block) when the FIS is the data format, and writing a special tag to the CDB and returning back to the error detecting step.

Claims (15)

1. A method for processing noise interference in a data accessing device with a SATA (Serial Advanced Technology Attachment) interface, the method comprising:

an error detecting step for detecting whether there is a CRC (Cyclic Redundancy Check) error, whether an reception error primitive (R_ERR primitive) is received, whether an improper primitive is received, or whether a LINK layer error is detected;

a type detecting step for detecting whether an FIS (Frame Information Structure) is a data type FIS;

a step for detecting whether the FIS is a ATAPI CDB (Command Descriptor Block) when the FIS is the data type; and

a step for setting a special mark on the CDB, or on any ATAPI Register if the FIS contains a CDB when there is an error.

2. The method according to claim 1 , wherein the method is used in a bridge solution, which connects a device with the serial ATA interface to a device with the parallel ATA interface.

3. The method according to claim 2 , further comprising:

a step for detecting whether it is a DMA (Direct Memory Access) mode data transfer when the present data FIS does not contain the ATAPI CDB; and

a step for generating an erroneous CRC (Cyclic Redundancy Check) code when data is being sent to a device with a parallel ATA interface when it is a DMA mode data transfer.

4. The method according to claim 1 , further comprising, before the step of detecting whether it is a DMA mode data transfer, the steps of:

detecting whether the length of the payload of the present data FIS is correct when the FIS does not contain the ATAPI CDB; and

adjusting the length by inserting or discarding data so as to make the data length correctness when the data length of the FIS is incorrect.

5. The method according to claim 4 , wherein the method is used in a bridge solution, which connects a device with the serial ATA interface to a device with the parallel ATA interface.

6. The method according to claim 1 , wherein the error detecting step is performed in a link layer.

7. The method according to claim 6 , wherein the method is used in a bridge solution, which connects a device with the serial ATA interface to a device with the parallel ATA interface.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 060646 FRAME: 0916. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 23, 2022
From: FORTIETH FLOOR, LLC
To: HAMILCAR BARCA IP LLC
Reel/Frame 061301/0567 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2022
From: FORTIETH FLOOR, LLC
To: HANNIBAL BARCA IP LLC
Reel/Frame 060646/0916 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2021
From: MEDIATEK INC.
To: FORTIETH FLOOR LLC
Reel/Frame 058342/0953 →