Nonvolatile semiconductor memory
View Patent ↗A nonvolatile semiconductor memory in which the area of each memory cell is small and which can perform high-speed operation with accuracy. A pair of honeycomb-like diffusion layers which are deviated from each other by a quarter-pitch are formed. Memory transistors (MemoryTr) and select transistors (SelectTr) are formed at portions where a pair of adjacent word lines pass over one diffusion layer and at portions where another pair of adjacent word lines pass over the other diffusion layer. In this case, the memory transistors and the select transistors are arranged so as to form a memory cell between a pair of bit lines connected to each diffusion layer. As a result, though the select transistors are located, many memory cells can be arranged like an array in a small layout area.
1. A nonvolatile semiconductor memory comprising
a plurality of diffusion layers formed in a semiconductor substrate and each having a shape of a honeycomb; and
memory transistors and select transistors each having a source region and a drain region in one of the plurality of diffusion layers.
2. The nonvolatile semiconductor memory according to claim 1 , wherein one diffusion layer is deviated from a second diffusion layer adjacent to the one diffusion layer by a quarter-pitch.
3. The nonvolatile semiconductor memory according to claim 1 , further comprising word lines which pass over plural portions of the plurality of diffusion layers, wherein one of the memory transistors and the select transistors using the word lines as gates are formed over each of the plural portions of the plurality of diffusion layers.
4. The nonvolatile semiconductor memory according to claim 3 , wherein two word lines which do not cross are located for each of the plurality of diffusion layers.
5. The nonvolatile semiconductor memory according to claim 3 , wherein at operation time voltage is applied to each of the word lines which pass over the plural portions of the plurality of diffusion layers.
6. The nonvolatile semiconductor memory according to claim 3 , wherein:
each of the memory transistors includes a floating gate which is located between the semiconductor substrate and one of the word lines and which is covered with an insulating film; and
each of the select transistors includes an insulating film between the semiconductor substrate and one of the word lines.
7. The nonvolatile semiconductor memory according to claim 1 , wherein:
a plurality of memory transistors share a combination region of one of the plurality of diffusion layers as source regions or drain regions;
a plurality of select transistors share a second combination region nearest the combination region as one of source regions and drain regions; and
a memory cell includes a combination of a memory transistor and a select transistor located between the combination region and the second combination region.
8. The nonvolatile semiconductor memory according to claim 7 , wherein bit lines are connected to the combination region and the second combination region of each of the plurality of diffusion layers.
9. The nonvolatile semiconductor memory according to claim 1 , wherein a memory transistor and a select transistor which have source regions and drain regions in one of the plurality of diffusion layers and a memory transistor and a select transistor which have source regions and drain regions in another of the plurality of diffusion layers are alternately made to operate.