Latch circuit and semiconductor integrated circuit having the same

1. A latch circuit comprising:

first and second inverter circuits cross-connected to each other;

a third inverter circuit for receiving an output from the first inverter circuit to output a logically inverted value of the output;

a switching element connected between an output terminal of the second inverter circuit and an output terminal of the third inverter circuit; and

a capacitor element connected between the output terminal of the third inverter circuit and a constant reference voltage node.

2. The latch circuit according to claim 1 , comprising:

a fourth inverter circuit for receiving an output from the second inverter circuit to output a logically inverted value of the output;

a switching element connected between the output terminal of the first inverter circuit and an output terminal of the fourth inverter circuit; and

a capacitor element connected between the output terminal of the fourth inverter circuit and the constant reference voltage node.

3. The latch circuit according to claim 1 , wherein the third inverter circuit is a tristate inverter circuit.

4. The latch circuit according to claim 1 , wherein the switching element is a MOS transistor switch.

5. The latch circuit according to claim 1 , wherein the switching element is a transfer gate.

6. The latch circuit according to claim 1 , wherein the capacitor element is a trench capacitor element.

7. The latch circuit according to claim 1 , wherein the capacitor element is a MOS capacitor.

8. A semiconductor integrated circuit including the latch circuit according to claim 1 , wherein the capacitor element is arranged to fill an empty space in the semiconductor integrated circuit.

9. A semiconductor integrated circuit comprising:

the latch circuit according to claim 1 ;

a clock gate circuit for controlling the presence/absence of outputting of an input clock signal on the basis of a control signal; and

an input control circuit for controlling the presence/absence of inputting of a data signal to the latch circuit in synchronism with an output signal from the clock gate circuit,

wherein the switching element operates in response to the control signal.

10. A semiconductor integrated circuit comprising:

the latch circuit according to claim 1 ; and

a switching control circuit for controlling a switching operation of the switching element in synchronism with switching of operation frequencies of the latch circuit.

11. A semiconductor integrated device comprising:

the latch circuit according to claim 1 ; and

a switching control circuit for controlling a switching operation of the switching element in synchronism with switching of operation voltages of the latch circuit.

12. A semiconductor integrated circuit comprising:

the latch circuit according to claim 1 ; and

a switching control circuit for detecting switching of operation voltages applied to the latch circuit to control the switching element to an ON state during a switching period.

13. A static semiconductor memory comprising the latch circuit according to claim 1 .

14. A master-slave-type flip-flop circuit comprising the latch circuit according to claim 1 as at least one of a master latch circuit and a slave latch circuit.

15. An information appliance comprising the latch circuit according to claim 1 .

16. A communication appliance comprising the latch circuit according to claim 1 .

17. An AV appliance comprising the latch circuit according to claim 1 .

18. A mobile appliance comprising the latch circuit according to claim 1 .