Devices, systems, and methods regarding a PLC system fault
View Patent ↗A method for providing a signal indicative of a set single bit flag, which is set for a scan cycle responsive to a detection of a fault in an Input/Output (I/O) device of a programmable logic controller (PLC) system or an I/O interface of the PLC system. Numerous other aspects are provided.
1. A method comprising:
providing a signal indicative of a set single bit flag, wherein:
said flag is set for a first scan cycle in response to a detection of a fault in an Input/Output (I/O) device of a programmable logic controller (PLC) system or an I/O interface of said PLC system, and said flag is promptly reset at a conclusion of said first scan cycle; and
said flag is set for a second scan cycle in response to a determination that said fault has been cleared, and said flag is promptly reset at a conclusion of said second scan cycle.
2. The method of claim 1 , further comprising:
detecting said fault.
3. The method of claim 1 , further comprising:
determining that said fault has been cleared.
4. The method of claim 1 , further comprising:
analyzing a message indicative of said fault; and
recording information related to said fault in an entry in a log.
5. The method of claim 1 , further comprising:
automatically receiving said signal indicative of said flag at a user control program of a PLC of said PLC system, said user control program written in an International Electrotechnical Commission (IEC) standard 1131-3 compliant language.
6. The method of claim 1 , further comprising:
automatically analyzing said signal indicative of said flag via a user control program of a PLC of said PLC system, said user control program written in an International Electrotechnical Commission (IEC) standard 1131-3 compliant language.
7. The method of claim 1 , further comprising:
automatically responding, via a rule based action, to said signal indicative of said flag by a user control program of a PLC of said PLC system, said user control program written in an International Electrotechnical Commission (IEC) standard 1131-3 compliant language.
8. The method of claim 1 , further comprising:
automatically determining a history of status changes of said flag via a user control program of a PLC of said PLC system, said user control program written in an International Electrotechnical Commission (IEC) standard 1131-3 compliant language.
9. The method of claim 1 , further comprising:
resetting said flag for only said second scan cycle responsive to said determination that said fault has been cleared.
10. The method of claim 1 , further comprising:
automatically creating an event, via PLC firmware, at a PLC of said PLC system.
11. The method of claim 1 , further comprising:
responsive to said flag, automatically causing a system interrupt to be executed, via PLC firmware, at a PLC of said PLC system.
12. The method of claim 1 , further comprising:
responsive to said flag, automatically causing an object block to be executed, via PLC firmware, at a PLC of said PLC system.
13. The method of claim 1 , further comprising:
responsive to said flag, automatically creating a diagnostic error, via PLC firmware, at a PLC of said PLC system.
14. The method of claim 1 , wherein said fault is detected via a cyclical redundancy check by said I/O device.
15. The method of claim 1 , wherein said fault is detected via a cyclical redundancy check in a message transmitted from said I/O device.
16. The method of claim 1 , wherein said fault is detected via a cyclical redundancy check in a message transmitted to said I/O interface.
17. The method of claim 1 , wherein said fault is detected via a cyclical redundancy check by said I/O device of I/O device firmware.
18. A machine-readable medium comprising machine instructions for activities comprising:
providing a signal indicative of a set single bit flag, wherein:
said flag is set for a first scan cycle in response to a detection of a fault in an Input/Output (I/O) device of a programmable logic controller (PLC) system or an I/O interface of said PLC system, and said flag is promptly reset at a conclusion of said first scan cycle; and
said flag is set for a second scan cycle in response to a determination that said fault has been cleared, and said flag is promptly reset at a conclusion of said second scan cycle.
19. A system comprising:
a circuit adapted to provide a signal indicative of a set single bit flag, wherein: said flag is set for a first scan cycle in response to a detection of a fault in an Input/Output (I/O) device of a programmable logic controller (PLC) system or an I/O interface of said PLC system, and said flag is promptly reset at a conclusion of said first scan cycle; and
said flag is set for a second scan cycle in response to a determination that said fault has been cleared, and said flag is promptly reset at a conclusion of said second scan cycle.