Cascode current sensor for discrete power semiconductor devices
View Patent ↗A cascode current sensor includes a main MOSFET and a sense MOSFET. The drain terminal of the main MOSFET is connected to a power device whose current is to be monitored, and the source and gate terminals of the main MOSFET are connected to the source and gate terminals, respectively, of the sense MOSFET. The drain voltages of the main and sense MOSFETs are equalized, in one embodiment by using a variable current source and negative feedback. The gate width of the main MOSFET is typically larger than the gate width of the sense MOSFET. Using the size ratio of the gate widths, the current in the main MOSFET is measured by sensing the magnitude of the current in the sense MOSFET. Inserting the relatively large MOSFET in the power circuit minimizes power loss.
1. A combination comprising:
a power semiconductor device connected in a power circuit; and
a cascode current sensor for measuring a current in the power circuit, the cascode current sensor being connected in series with the power semiconductor device and comprising:
a main MOSFET, the source and drain terminals of the main MOSFET being connected in the power circuit; and
a sense MOSFET, a source terminal of the sense MOSFET being connected to the source terminal of the main MOSFET, the respective gate terminals of the main and sense MOSFETs being connected to a gate terminal of the current sensor, the main and sense MOSFETs together forming a current mirror arrangement.
2. The combination of claim 1 wherein a main voltage at a drain terminal of the main MOSFET is equal to a sense voltage at a drain terminal of the sense MOSFET.
3. The combination of claim 1 comprising a current sense and bias circuit for maintaining the respective voltages at the drain terminals of the main and sense MOSFETs at the same value.
4. The combination of claim 3 wherein the current sense and bias circuit comprises:
an amplifier having a first input terminal connected to the drain terminal of the main MOSFET and a second input terminal connected to the drain terminal of the sense MOSFET; and
a first variable current source connected to deliver a current through the sense MOSFET, an output terminal of the amplifier being connected to an input terminal of the first variable current source.
5. The combination of claim 4 wherein each of the main and sense MOSFETs comprises a P-channel MOSFET and the cascode current sensor is connected on the high side of the power semiconductor device.
6. The combination of claim 4 wherein the current sense and bias circuit comprises a second variable current source, the output terminal of the amplifier being connected to an input terminal of the second variable current source, an output terminal of the second variable current source being connected to a sense current terminal of the cascode current sensor.
7. The combination of claim 4 wherein the first variable current source comprises a first current source MOSFET and a second current source MOSFET, a gate terminal of the first current source MOSFET and a gate terminal and a drain terminal of the second current source MOSFET being connected to the output terminal of the amplifier, the respective source terminals of the first and second current source MOSFETs being connected to a first voltage source, the drain terminal of the first current source MOSFET being connected to the sense MOSFET.
8. The combination of claim 6 wherein the second variable current source comprises a third current source MOSFET having a gate terminal connected to the output terminal of the amplifier, a source terminal connected to the first voltage source, and a drain terminal connected to the sense current terminal of the cascode current sensor.
9. The combination of claim 3 wherein the current sense and bias circuit comprises:
an analog multiplexer set to alternately sample the voltages at the drain terminals of the main and sense MOSFETs, respectively;
an analog-to-digital converter having an input terminal connected to the analog multiplexer;
a digital comparator having an input terminal connected to an output terminal of the analog-to-digital converter;
a digital-to-analog converter having an input terminal connected to an output terminal of the digital comparator; and
a first variable current source connected to deliver a current through the sense MOSFET, an output terminal of the first variable current source being connected to an input terminal of the first variable current source.
10. The combination of claim 9 wherein the current sense and bias circuit comprises a second variable current source, the output terminal of the digital-to-analog converter being connected to an input terminal of the second variable current source, an output terminal of the second variable current source being connected to a sense current terminal of the cascode current sensor.
11. The combination of claim 1 comprising a boost converter, wherein the power semiconductor device comprises a power MOSFET and the combination further comprises:
a pulse-width modulator having an input terminal connected via an over-current shutdown comparator to a current sense terminal of the cascode current sensor and an output terminal connected to a gate terminal of the power MOSFET;
an inductor connected in the power circuit;
a rectifier diode connected between a node in the power circuit located between the inductor and the power MOSFET and an output terminal of the boost converter.
12. The combination of claim 1 comprising a Buck converter, wherein the power semiconductor device comprises a power MOSFET and the combination further comprises:
a pulse-width modulator having an input terminal connected via an over-current shutdown comparator to a current sense terminal of the cascode current sensor and an output terminal connected so as to drive a gate terminal of the power MOSFET;
a rectifier diode connected in the power circuit;
an inductor connected between a node in the power circuit located between the rectifier diode and the power MOSFET and an output terminal of the Buck converter.
13. The combination of claim 1 comprising a totem-pole push-pull circuit, the combination further comprising a second power semiconductor device connected in the power circuit; and a load connected to a node located in the power circuit between the first and second semiconductor power devices.