Memory controller configurable to allow bandwidth/latency tradeoff
A memory controller includes a plurality of channel control circuits. Each of the plurality of channel control circuits is coupled to a respective one of a plurality of channels which are coupled to a memory system. The plurality of channel control circuits are coupled to receive an indication of whether or not the plurality of channels are ganged. Data is transferred for a first command on each of the plurality of channels responsive to the indication indicating that the plurality of channels are ganged. Responsive to the indication indicating that the plurality of channels are not ganged, data is transferred for the first command on a selected channel of the plurality of channels. In some embodiments, the memory controller may be integrated with one or more processors.
1. An apparatus comprising:
a first control circuit coupled to a first data path;
a second control circuit coupled to a second data path;
a decode circuit coupled to receive an indication of whether or not a first memory channel and a second memory channel are ganged or not ganged and the decode circuit also coupled to receive a command to perform an access to a memory;
a channel configuration register coupled to store the indication; and
a data normalizer circuit coupled to the first and second control circuits respectively via the first and second data paths, the data normalizer circuit also coupled to the first memory channel and the second memory channel, wherein the data normalizer circuit to route data between the first data path and the memory via both the first and second memory channels when the indication indicates that the memory channels are ganged, but the data normalizer circuit to route data between the first data path and the first memory channel and to route data between the second data path and the second memory channel when the indication indicates that the memory channels are not ganged.
2. The apparatus of claim 1 , wherein the first data path operates at a double data rate (DDR) when the memory channels are ganged.
3. The apparatus of claim 1 , wherein each of the first and second memory channels is to transfer data at 32-bit double data rate (DDR) and the first data path is to transfer data at 64-bit DDR, when the memory channels are ganged.
4. The apparatus of claim 1 , wherein each of the first and second memory channels is to transfer data at 32-bit double data rate (DDR), such that when the memory channels are not ganged, the first data path is to transfer data to and from the data normalizer at 64-bit single data rate (SDR) and the second data path is to transfer data to and from the data normalizer at 64-bit SDR.
5. The apparatus of claim 1 , wherein when the memory channels are ganged, the data transfer on the first and second memory channels are to a same memory device.
6. The apparatus of claim 1 , wherein when the memory channels are not ganged, the data transfer on the first and second memory channels are to a different memory device.
7. The apparatus of claim 1 , wherein the first and second memory channels operate at a given bit width to transfer data between the data normalizer and the memory, in which the data normalizer is to normalize data for transfer between the first and second memory channels and the first data path that has twice the given bit width.
8. The apparatus of claim 1 , wherein the first and second memory channels operate at a particular bit width and particular data rate to transfer data between the data normalizer and the memory, in which when the first data path operates at twice the particular bit width and at the same particular data rate, the memory channels are ganged so that the data normalizer transfers data between the first and second memory channels and the first data path, but when the first data path operates at twice the particular bit width and at half the particular data rate, the memory channels are not ganged so that the data normalizer transfers data respectively between the first and second memory channels and the first and second data paths.
9. A method comprising:
decoding a received indication that indicates whether or not a first memory channel and a second memory channel are ganged or not ganged, the first and second memory channels coupled to a memory;
storing the indication;
decoding a received command to perform an access to a memory; and
normalizing data between the first and second memory channels for transfer to and from first and second data paths, wherein the normalizing routes data between the first data path and the memory via both the first and second memory channels when the indication indicates that the memory channels are ganged, but the normalizing routes data between the first data path and the first memory channel and routes data between the second data path and the second memory channel when the indication indicates that the memory channels are not ganged.
10. The method of claim 9 , further comprising transferring data at a double data rate (DDR) on the first data path when the memory channels are ganged.
11. The method of claim 9 , further comprising transferring data at 32-bit double data rate (DDR) for each of the first and second memory channels and transferring data at 64-bit DDR for the first data path, when the memory channels are ganged.
12. The method of claim 9 , further comprising transferring data at 32-bit double data rate (DDR) for each of the first and second memory channels, such that when the memory channels are not ganged, the first data path transfers data at 64-bit single data rate (SDR) and the second data path transfers data at 64-bit SDR.
13. The method of claim 9 , wherein when the memory channels are ganged, the data transfer on the first and second memory channels are to a same memory device.
14. The method of claim 9 , wherein when the memory channels are not ganged, the data transfer on the first and second memory channels are to a different memory device.
15. The method of claim 9 , further comprising transferring data on the first and second memory channels at a given bit width, in which the normalizing normalizes data for transfer between the first and second memory channels and the first data path that has twice the given bit width.
16. The method of claim 9 , further comprising transferring data on the first and second memory channels at a particular bit width and particular data rate, in which when the first data path operates at twice the particular bit width and at the same particular data rate, the memory channels are ganged to transfer data between the first and second memory channels and the first data path, but when the first data path operates at twice the particular bit width and at half the particular data rate, the memory channels are not ganged to transfer data respectively between the first and second memory channels and the first and second data paths.