IP Library Granted Patent US 8,299,626
Granted Patent B2
US 8,299,626 · App. 11/894,036 · Granted Oct 30, 2012

Microelectronic package

Assignee: Tessera, Inc.
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Quick Facts
Patent No.
US 8,299,626
App. No.
11/894,036
Filed
Aug 16, 2007
Granted
Oct 30, 2012
Kind
B2
Art Unit
2811
USPC
257/777
Abstract

A microelectronic package includes a lower unit having a lower unit substrate with conductive features and a top and bottom surface. The lower unit includes one or more lower unit chips overly/ing the top surface of the lower unit substrate that are electrically connected to the conductive features of the lower unit substrate. The microelectronic package also includes an upper unit including an upper unit substrate having conductive features, top and bottom surfaces and a hole extending between such top and bottom surfaces. The upper unit further includes one or more upper unit chips overlying the top surface of the upper unit substrate and electrically connected to the conductive features of the upper unit substrate by connections extending within the hole. The upper unit may include an upper unit encapsulant that covers the connections of the upper unit and the one or more upper unit chips.

Claims (12)

1. A microelectronic package comprising:

a first microelectronic element having a plurality of contacts;

a second microelectronic element having a plurality of contacts, said second microelectronic element disposed under said first microelectronic element, such that said contacts of said first microelectronic element are exposed beyond an edge of said second microelectronic element;

a dielectric element disposed under said second microelectronic element, said dielectric element having a first face, a second face remote from said first face, conductive features including contact pads exposed at said second face, and a hole extending from said first face to said second face;

a first set of electrically conductive connection elements extending between said plurality of contacts of said first microelectronic element and at least some of said conductive features of said dielectric element; and

a second set of electrically conductive connection elements extending between said plurality of contacts of said second microelectronic element and at least some of said conductive features of said dielectric element;

wherein at least some of said first set of electrically conductive connection elements and at least some of said second set of electrically conductive connection elements extend through said hole of said dielectric element and are connected to said contact pads,

wherein an encapsulant is disposed over said first and second microelectronic elements and said first and second sets of electrically conductive connection elements, and

wherein said encapsulant overlying said first microelectronic element has a first height above said first surface of said dielectric element and said encapsulant overlying said second microelectronic element has a second height above said first surface of said dielectric element, the first height being greater than the second height.

2. The microelectronic package according to claim 1 , wherein a height of said encapsulant at said first and second sets of electrically conductive connection elements is greater than a height of said encapsulant over said first and second microelectronic elements.

3. The microelectronic package according to claim 1 , further comprising a third microelectronic element positioned over said first and second microelectronic elements, and a fourth microelectronic element positioned over said first, second and third microelectronic elements, said dielectric element having an outer edge, and each of said first, third and fourth microelectronic elements having an edge, said edge of said fourth microelectronic element being more proximate said outer edge of said dielectric element than said edges of said first, second, and third microelectronic elements.

4. The microelectronic assembly as claimed in claim 1 , wherein said edge is a first edge, and a step is formed in the encapsulant at a point wherein a second edge of the second microelectronic element, which is opposed to said first edge, extends beyond an edge of the first microelectronic element.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2008
From: MOHAMMED, ILYAS; HABA, BELGACEM; MORAN, SEAN; WANG, WEI-SHUN; CHAU, ELLIS; WADE, CHRISTOPHER
To: TESSERA, INC.
Reel/Frame 020531/0089 →
Continuity (1)
Related Publication 20090045524A1 · Feb 19, 2009