Multiple die paddle leadframe and semiconductor device package
View Patent ↗A leadframe and semiconductor device package with multiple semiconductor device die paddles for accepting multiple semiconductor devices is disclosed, wherein the leadframe increases semiconductor device density and reduces cost by integrating the multiple dies into a semiconductor device package with a relatively small footprint. The leadframe may include at least one full-metal die paddle and at least one reduced-metal die paddle, which may form a unified or hybrid die paddle. The leadframe may enable electrical coupling of multiple semiconductor devices to a common leadfinger and/or die paddle, where internal leadfingers coupled to the common leadfingers and/or die paddles may receive the electrical coupling means from the semiconductor device. Surfaces of one or more die paddles of the leadframe may be exposed to the outside of the semiconductor device package to enable electrical testing of and/or provide heat dissipation from one or more of the semiconductor devices attached to the leadframe.
1. An apparatus comprising:
a full-metal die paddle comprising a mounting surface to accept a first semiconductor device, wherein a surface area of the full-metal die paddle mounting surface is larger than a surface area of a mounting surface of the first semiconductor die;
a reduced-metal die paddle comprising a mounting surface to accept a second semiconductor device, wherein a surface area of the reduced-metal die paddle mounting surface is smaller than a surface area of a mounting surface of the second semiconductor die;
a frame having a perimeter around the full-metal die paddle and the reduced-metal die paddle;
a plurality of leadfingers extending inward from the frame; and
wherein the full-metal die paddle mounting surface and the reduced-metal die paddle mounting surface are coplanar in a first plane and directly adjoined in the first plane by a straight member of the leadframe extending between the full-metal die paddle mounting surface and the reduced-metal die paddle mounting surface to form a unified die paddle.
2. The apparatus of claim 1 , wherein the surface area of the reduced-metal die paddle mounting surface is smaller than the surface area of the mounting surface of the first semiconductor device.
3. The apparatus of claim 1 , wherein the reduced-metal die paddle mounting surface comprises a plurality of adjoining circular portions.
4. The apparatus of claim 1 further comprising:
at least one additional die paddle comprising a mounting surface to accept an additional semiconductor device and a second surface to perform electrical testing of the additional semiconductor device.
5. The apparatus of claim 1 , wherein the full-metal die paddle comprises a surface to provide heat dissipation from the first semiconductor device.
6. The apparatus of claim 1 , wherein at least one of the plurality of leadfingers comprises:
a first surface to couple to a semiconductor device; and
a second surface opposing the first surface and to provide electrical access to the leadfinger from outside of a semiconductor device package incorporating the leadframe.
7. The apparatus of claim 1 , wherein at least one of the plurality of leadfingers comprises:
a first surface to couple to a semiconductor device; and
a second surface opposing the first surface, wherein the second surface is etched to limit electrical access to the leadfinger from outside of a semiconductor device package incorporating the leadframe.
8. A multi-die semiconductor device package comprising:
a leadframe comprising:
a full-metal die paddle comprising a mounting surface;
a reduced-metal die paddle comprising a mounting surface; and
a frame having a perimeter around the full-metal die paddle and the reduced-metal die paddle;
a plurality of leadfingers extending inward from the frame;
wherein the full-metal die paddle mounting surface and the reduced-metal die paddle mounting surface are coplanar in a first plane and directly adjoined in the first plane by a straight member of the leadframe extending between the full-metal die paddle mounting surface and the reduced-metal die paddle mounting surface to form a unified die paddle;
a first semiconductor device mounted on the full-metal die paddle mounting surface, wherein a surface area of the full-metal die paddle mounting surface is larger than a surface area of a mounting surface of the first semiconductor die; and
a second semiconductor device mounted on the reduced-metal die paddle mounting surface, wherein a surface area of the reduced-metal die paddle mounting surface is smaller than a surface area of a mounting surface of the second semiconductor die such that the second semiconductor device overhangs the reduced-metal die paddle mounting surface.
9. The multi-die semiconductor device package of claim 8 , wherein the surface area of the reduced-metal die paddle mounting surface is smaller than the surface area of the mounting surface of the first semiconductor device.
10. The multi-die semiconductor device package of claim 8 , wherein the reduced-metal die paddle mounting surface comprises a plurality of adjoining circular portions.
11. The multi-die semiconductor device package of claim 8 , wherein the leadframe further comprises:
at least one additional die paddle comprising a mounting surface to accept an additional semiconductor device and a second surface to perform electrical testing of the additional semiconductor device.
12. The multi-die semiconductor device package of claim 11 , wherein the additional semiconductor device is electrically coupled to at least two die paddles with respective surfaces to perform electrical testing of the additional semiconductor device.
13. The multi-die semiconductor device package of claim 8 , wherein the full-metal die paddle comprises a surface to provide heat dissipation from the first semiconductor device.
14. The multi-die semiconductor device package of claim 8 , wherein at least one of the plurality of leadfingers comprises:
a first surface to couple to a semiconductor device; and
a second surface opposing the first surface and to provide electrical access to the leadfinger from outside of the semiconductor device package.
15. The multi-die semiconductor device package of claim 8 , wherein at least one of said plurality of leadfingers comprises:
a first surface to couple to a semiconductor device; and
a second surface opposing the first surface, wherein the second surface is etched to limit electrical access to the leadfinger from outside of the semiconductor device package.