IP Library Granted Patent US 7,351,995
Granted Patent B2
US 7,351,995 · App. 11/894,938 · Granted Apr 1, 2008

Floating body germanium phototransistor having a photo absorption threshold bias region

Assignee: Sharp Laboratories of America, Inc.
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Quick Facts
Patent No.
US 7,351,995
App. No.
11/894,938
Granted
Apr 1, 2008
Kind
B2
Abstract

A floating body germanium (Ge) phototransistor with a photo absorption threshold bias region, and an associated fabrication process are presented. The method includes: providing a p-doped Silicon (Si) substrate; selectively forming an insulator layer overlying a first surface of the Si substrate; forming an epitaxial Ge layer overlying the insulator layer; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers; forming source/drain (S/D) regions in the Ge layer; and, forming a photo absorption threshold bias region in the Ge layer, adjacent the channel region. In one aspect, the second S/D region has a length, longer than the first S/D length. The photo absorption threshold bias region underlies the second S/D region. Alternately, the second S/D region is separated from the channel by an offset, and the photo absorption threshold bias region is the offset in the Ge layer, after a light p-doping.

Claims (46)

1. A floating body Germanium (Ge) phototransistor with a photo absorption threshold bias region, the phototransistor comprising:

a p-doped Silicon (Si) substrate;

an insulator layer overlying a first surface of the Si substrate;

an epitaxial Ge layer overlying the insulator layer;

a channel region in the Ge layer;

a gate dielectric, gate electrode, and gate spacers overlying the channel region;

first and second source/drain (S/D) regions in the Ge layer; and,

a photo absorption threshold bias region in the Ge layer, adjacent the channel region.

2. The phototransistor of claim 1 wherein the epitaxial Ge layer has a thickness in the range of about 300 to 1000 nanometers (nm).

3. The phototransistor of claim 1 wherein the insulator layer is a silicon nitride layer with a top surface;

wherein the Si substrate includes a second surface adjacent the first surface; and,

the phototransistor further comprising:

silicon oxide overlying the Si substrate second surface.

4. The phototransistor of claim 3 further comprising:

a p-doped region in the Ge layer, immediately overlying the silicon nitride top surface.

5. The phototransistor of claim 3 wherein the first S/D region approximately overlies the Si substrate second surface and has a first length;

wherein the second S/D region has a second length, longer than the first length; and,

wherein the photo absorption threshold bias region in the Ge layer underlies the second S/D region.

6. The phototransistor of claim 3 wherein the first S/D region approximately overlies the Si substrate second surface; and,

wherein the photo absorption threshold bias region in the Ge layer includes a p-doped offset separating the second S/D region from the channel.

7. The phototransistor of claim 6 wherein the second S/D region has a channel-side edge offset from the channel region by a distance no larger than d, where d is calculated as follows:

d

=

2

ɛ

(

V

D

-

V

DSAT

)

q

N

where ε is the dielectric constant of the germanium;

where N is the channel doping density; and,

where V D and V DSAT are the second S/D bias voltage and saturation voltage at the operational gate bias voltage, respectively.

8. The phototransistor of claim 1 wherein the insulator layer overlying the Si substrate has a thickness in the range of about 10 to 500 nm.

9. The phototransistor of claim 1 wherein the gate dielectric and gate spacers are formed from wide bandgap materials.

10. The phototransistor of claim 9 wherein the gate dielectric is a material selected from the group consisting of SiO 2 , GeO 2 , Al 2 O 3 , HfO 2 , ZrO 2 , TiO 2 , Ta 2 O 5 , and combinations of the above-mentioned materials;

wherein the gate electrode is a material selected from the group consisting of polycrystalline Ge, polycrystalline SiGe, and polysilicon; and,

wherein the gate spacers are a material selected from the group consisting of SiO 2 and Si 3 N 4 .

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2017
From: SHARP CORPORATION AKA SHARP KABUSHIKI KAISHA
To: MICROSOFT TECHNOLOGY LICENSING, LLC
Reel/Frame 044410/0751 →
NUNC PRO TUNC ASSIGNMENT Recorded Oct 10, 2016
From: SHARP LABORATORIES OF AMERICA, INC.
To: SHARP KABUSHIKI KAISHA AKA SHARP CORPORATION
Reel/Frame 039973/0362 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 18, 2015
From: HSU, SHENG TENG; LEE, JONG-JAN; MAA, JER-SHEN; TWEET, DOUGLAS J.
To: SHARP LABORATORIES OF AMERICA, INC.
Reel/Frame 035863/0094 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2008
From: SHARP LABORATORIES OF AMERICA INC.
To: SHARP KABUSHIKI KAISHA
Reel/Frame 020995/0876 →
Continuity (3)
Division 1126119100 · Oct 28, 2005
Continuation In Part 1117403500 · Jul 1, 2005
Related Publication 20070290288A1 · Dec 20, 2007