Granted Patent B2

US 8,161,311 · App. 11/895,048 · Granted Apr 17, 2012

Abstract

Claims (33)

1. A fault-tolerant clocking apparatus comprising:

a first process controller configured to generate a first digital data value; a data control port in data communication with the process controller configured to receive the first digital data value and generate a first formatted data value in response to the first digital data value; and

a core clock synthesizer circuit in data communication with the data control port configured to receive the first formatted data value and a first clock signal and generate an output clock signal of a predetermined frequency within a predetermined range of frequency values in response to the first formatted data value and the first clock signal.

2. A method of fault-tolerant clocking comprising the steps of:

generating, by a first process controller, a first digital data value;

receiving the first digital data value in a data control port;

generating a first formatted data value in response to the first digital data value;

receiving the first formatted data value and a first clock signal in a core clock synthesizer circuit; and

generating an output clock signal of a constantly varying frequency within a predetermined range of frequency values in response to the first formatted data value and the first clock signal.

3. A method of fault-tolerant and spread spectrum clocking comprising the steps of:

generating, by a first process controller, a first digital data stream;

receiving the first digital data stream, a first input reference signal and a first clock signal in a master clock synthesizer circuit;

generating a first output clock signal of a varying frequency by the master clock synthesizer circuit in response to the first digital data stream and the first clock signal;

receiving the first output clock signal of the master clock synthesizer circuit and a second clock signal in a slave clock synthesizer circuit;

generating a second output clock signal of varying frequency by the slave clock synthesizer circuit in response to the first output clock signal of the master clock synthesizer circuit and the second clock signal; and

transmitting the second output clock signal of the slave clock synthesizer circuit to the master clock synthesizer circuit as the first input reference signal.

4. The apparatus of claim 3 , further comprising a second process controller configured to generate a second digital data stream.

5. The apparatus of claim 3 wherein the frequency is constantly varied.

6. A fault-tolerant and spread spectrum clocking apparatus comprising:

a first clock synthesizer circuit configured to receive a first input reference signal, a first digital data value and a first clock signal and generate a first output clock signal of a varying frequency in response to the first digital data value and the first clock signal, and

a second clock synthesizer circuit in data communication with the first clock synthesizer circuit configured to receive the first output clock signal of the first clock synthesizer circuit and a second clock signal and generate a varying second output clock signal in response to the first output clock signal and the second clock signal, wherein the first clock synthesizer circuit is further configured to receive the second output clock signal as the first input reference signal.

7. The apparatus of claim 6 , wherein the second data control port is configured to receive the second digital data stream and generate plurality of second formatted data values in response to the second digital data stream.

8. A method of fault-tolerant and spread spectrum clocking comprising the steps of:

generating, by a first process controller, a first digital data stream having a plurality of values;

receiving the first digital data stream, a first input reference signal and a first clock signal in a master clock synthesizer circuit;

generating a first output clock signal of a varying frequency by the master clock synthesizer circuit in response to the first digital data stream and the first clock signal;

receiving the first output clock signal of the master clock synthesizer circuit and a second clock signal in a slave clock synthesizer circuit;

generating a second output clock signal of a varying frequency by the slave clock synthesizer circuit in response to the first output clock signal of the master clock synthesizer circuit and the second clock signal; and

transmitting the second output clock signal of the slave clock synthesizer circuit to the master clock synthesizer circuit as the first input reference signal.

9. A fault-tolerant and spread spectrum clocking apparatus comprising:

a first process controller configured to generate a first digital data stream having a plurality of values;

a first clock synthesizer circuit in data communication with the process controller, wherein the first clock synthesizer circuit further comprises a first data control port configured to receive the first digital data stream and generate a series of formatted data value in response to the first digital data stream, and a first core clock synthesizer circuit configured to receive a first input reference signal, the series of formatted data values and a first clock signal and generate an output clock signal of a varying frequency within a predetermined range of frequency values in response to the series of formatted data values and the first clock signal; and

a second clock synthesizer circuit, wherein the second clock synthesizer circuit further comprises a second data control port, and a second core clock synthesizer circuit configured to receive the first output clock signal and a second clock signal and generate a varying second output clock signal in response to the first output clock signal and the second clock signal, wherein the first clock synthesizer circuit is further configured to receive the second output clock signal as the first input reference signal.

Assignments (7)