Method and signal control system providing fast transitions in an oscillating signal
View Patent ↗In one embodiment, a signal control system has a signal output and includes: 1) a phase-locked loop (PLL) having a voltage-controlled oscillator (VCO), a phase error detector, an oscillating output coupled to the signal output of the signal control system, and a programmable frequency divider coupled in a feedback path between the oscillating output and the phase error detector; 2) at least one automatic level controller (ALC), coupled to the oscillating output; and 3) a plurality of switchable integrators, including first and second switchable integrators that are respectively coupled between the phase error detector and the VCO, and in the at least one ALC. Each of the switchable integrators is switchable between a narrow bandwidth mode that provides for stable operation of the signal control system, and a wide bandwidth mode that enables fast signal transitions at the signal output.
1. A signal control system having a signal output, the signal control system comprising:
a phase-locked loop (PLL) having a voltage-controlled oscillator (VCO), a phase error detector, an oscillating output coupled to the signal output of the signal control system, and a programmable frequency divider coupled in a feedback path between the oscillating output and the phase error detector;
at least one automatic level controller (ALC) coupled to the oscillating output of the PLL;
a plurality of switchable integrators, including first and second switchable integrators that are respectively coupled between the phase error detector and the VCO, and in the at least one ALC, wherein each of the switchable integrators is switchable between 1) a narrow bandwidth mode that provides for stable operation of the signal control system, and 2) a wide bandwidth mode that enables fast signal transitions at the signal output; and
a controller configured to,
in response to a signal transition request, i) open the PLL, ii) switch the switchable integrators from their narrow bandwidth modes to their wide bandwidth modes, iii) drive the VCO with a pre-tune voltage for a first predetermined time, and iv) program the frequency divider; and
after driving the VCO with the pre-tune voltage for the first predetermined time, close the PLL and switch the first and second switchable integrators to their narrow bandwidth modes.
2. The signal control system of claim 1 , wherein:
the VCO has an amplitude control input;
the at least one ALC comprises a first ALC coupled between the oscillating output of the VCO and the amplitude control input of the VCO; and
the second switchable integrator is coupled in the first ALC.
3. A signal control system having a signal output, the signal control system comprising:
a phase-locked loop (PLL) having a voltage-controlled oscillator (VCO), a phase error detector, an oscillating output coupled to the signal output of the signal control system, and a programmable frequency divider coupled in a feedback path between the oscillating output and the phase error detector, the VCO having an amplitude control input;
at least one automatic level controller (ALC) coupled to the oscillating output of the PLL, the at least one ALC including i) a first ALC coupled between the oscillating output of the VCO and the amplitude control input of the VCO, and ii) a second ALC coupled between the oscillating output of the VCO and the signal output of the signal control system; and
a plurality of switchable integrators, including first, second and third switchable integrators that are respectively coupled between i) the phase error detector and the VCO, ii) in the first ALC, and ii) in the second ALC, wherein each of the switchable integrators is switchable between 1) a narrow bandwidth mode that provides for stable operation of the signal control system, and 2) a wide bandwidth mode that enables fast signal transitions at the signal output.
4. The signal control system of claim 3 , further comprising a controller, configured to:
in response to a signal transition request,
open the PLL;
switch the switchable integrators from their narrow bandwidth modes to their wide bandwidth modes;
drive the VCO with a pre-tune voltage for a first predetermined time; and
program the frequency divider;
after driving the VCO with the pre-tune voltage for the first predetermined time,
close the PLL; and
switch the first switchable integrator to its narrow bandwidth mode, while the second and third switchable integrators remain in their wide bandwidth modes;
after the second switchable integrator has remained in its wide bandwidth mode for a second predetermined time, switching the second switchable integrator to its narrow bandwidth mode while the third switchable integrator remains in its wide bandwidth mode; and
after switching the second switchable integrator to its narrow bandwidth mode, switching the third switchable integrator to its narrow bandwidth mode.
5. The signal control system of claim 4 , wherein the controller comprises a number of timers, and wherein the controller switches the switchable integrators from their wide bandwidth modes to their narrow bandwidth modes in response to the number of timers.
6. The signal control system of claim 5 , wherein functions of the controller are implemented via firmware and a field-programmable gate array (FPGA), and wherein the number of timers are implemented by the FPGA.
7. The signal control system of claim 4 , wherein the controller is further configured to, in response to the signal transition request, i) compute an output level correction for the second ALC, and then ii) program the second ALC to provide the output level correction.
8. The signal control system of claim 4 , wherein the signal transition request consists of signal transition requests that exceed a threshold.
9. The signal control system of claim 1 , wherein the at least one ALC comprises an ALC coupled between the oscillating output of the VCO and the signal output of the signal control system.
10. The signal control system of claim 1 , further comprising:
a controller configured to switch the switchable integrators between their narrow bandwidth modes and their wide bandwidth modes, the controller comprising a number of timers, and the controller switching the switchable integrators from their wide bandwidth modes to their narrow bandwidth modes in response to the number of timers.
11. The signal control system of claim 10 , wherein the number of timers is implemented by a field-programmable gate array (FPGA).
12. The signal control system of claim 1 , wherein the controller is further configured to:
after driving the VCO with the pre-tune voltage for the first predetermined time,
switch the first switchable integrator to its narrow bandwidth mode while the second switchable integrator remains in its wide bandwidth mode; and
after the second switchable integrator has remained in its wide bandwidth mode for a second predetermined time, switch the second switchable integrator to its narrow bandwidth mode.
13. The signal control system of claim 1 , wherein the signal output is a radio frequency (RF) signal output.
14. The signal control system of claim 1 , wherein each of the switchable integrators comprises at least one capacitor that is switchable into and out of the switchable integrator.
15. The signal control system of claim 1 , wherein at least one of the plurality of switchable integrators comprises a plurality of feedback capacitors, wherein 1) in the narrow bandwidth mode, first and second feedback capacitors of the plurality of feedback capacitors are coupled in parallel, in a feedback path of the at least one of the plurality of switchable integrators, and 2) in the wide bandwidth mode, the first feedback capacitor is coupled in the feedback path, and the second feedback capacitor is charged to a voltage.
16. The signal control system of claim 15 , wherein, when in the wide bandwidth mode, the second feedback capacitor is charged to a voltage related to V 1 , where V 1 =A*V 2 +B, where V 2 is a voltage to which the first feedback capacitor is charged in the wide bandwidth mode, and where A and B are constants.
17. A method of providing fast signal transitions in an oscillating signal, comprising:
generating the oscillating signal via a phase-locked loop (PLL) having a voltage-controlled oscillator (VCO) and a programmable frequency divider;
automatically adjusting an amplitude of the oscillating output via at least one automatic level controller (ALC);
in response to a signal transition request,
opening the PLL;
switching each of a plurality of switchable integrators, including first and second switchable integrators that are respectively coupled in the PLL and the at least one ALC, from a narrow bandwidth mode to a wide bandwidth mode;
driving the VCO with a pre-tune voltage for a first predetermined time; and
programming the frequency divider;
after driving the VCO with the pre-tune voltage for the first predetermined time, closing the PLL; and
switching the first switchable integrator to its narrow bandwidth mode, while the second switchable integrator remains in its wide bandwidth mode; and
after the second switchable integrator has remained in its wide bandwidth mode for a second predetermined time, switching the second switchable integrator to its narrow bandwidth mode.
18. The method of claim 17 , wherein switching each of the plurality of switchable integrators comprises switching at least one capacitor into or out of each switchable integrator.
19. The method of claim 17 , further comprising, switching the switchable integrators from their high bandwidth modes to their low bandwidth modes in response to a number of timers implemented by a field-programmable gate array (FPGA).
20. The method of claim 19 , wherein the at least one ALC comprises a first ALC feeding the oscillating signal of the VCO back to an amplitude control input of the VCO, and a second ALC receiving the oscillating signal of the VCO and producing an amplified oscillating signal, the first ALC having the second switchable integrator coupled therein, and the second ALC having a third switchable integrator coupled therein, the method further comprising:
in response to the a signal transition request, i) computing an output level correction for the second ALC, and then ii) programming the second ALC to provide the output level correction; and
after switching the second switchable integrator to its narrow bandwidth mode, switching the third switchable integrator to its narrow bandwidth mode.
21. The method of claim 17 , wherein the signal transition request consists of signal transition requests that exceed a threshold.