III-nitride power semiconductor device
View Patent ↗A power semiconductor device that includes common conduction regions, charge compensation regions, each adjacent a respective common conduction region, and a stand off region over the common conduction regions and charge compensation regions.
1. A power semiconductor device comprising:
a common conduction region of a first conductivity disposed over a substrate;
a charge compensation region of a second conductivity adjacent said common conduction region, said charge compensation region disposed over a pillar of a growth inhibition material;
a stand off region of said first conductivity over said common conduction region and said charge compensation region;
a base region of said second conductivity over said stand off region;
a source region of said first conductivity over said base region.
2. The power semiconductor device of claim 1 , comprising another charge compensation region adjacent said common conduction region wherein said another charge compensation region is disposed over a respective pillar of a growth inhibition material.
3. The power semiconductor device of claim 1 , wherein said growth inhibition material is comprised of silicon dioxide.
4. The power semiconductor device of claim 1 , wherein said first conductivity is N-type and said second conductivity is P-type.
5. The power semiconductor device of claim 1 , wherein said first conductivity is P-type and said second conductivity is N-type.
6. The power semiconductor device of claim 1 , wherein said charge compensation region is an epitaxial body.
7. The power semiconductor device of claim 1 , wherein said common conduction region, said charge compensation region, said stand off region, said base region and said source region are each comprised of a respective III-nitride material.
8. The power semiconductor device of claim 1 , wherein said III-nitride material is comprised of GaN.
9. The power semiconductor device of claim 1 , further comprising a gate trench extending through said source region and said base region, a gate insulation body lining the sidewalls of said gate trench, a gate electrode inside said trench, a source electrode ohmically connected to said source region, and a drain electrode ohmically connected to said substrate.
10. A superjunction semiconductor device comprising:
a common conduction region of a first conductivity disposed over a substrate;
a charge compensation region of a second conductivity adjacent said common conduction region, said common conduction region comprising a first conductive region and a second conductive region formed on said first conductive region, the first and second conductive regions having different doping profiles; and
a pillar of a growth inhibition material disposed under said charge compensation region, said second conductive region rising from below a surface of said pillar to above said surface of said pillar.
11. The superjunction semiconductor device of claim 10 , wherein said first conductive region of has a higher conductivity than said second conductive region.
12. The superjunction semiconductor device of claim 10 , wherein said common conduction region, said charge compensation region, and a stand off region comprise a respective III-nitride material.
13. The superjunction semiconductor device of claim 10 , further comprising:
a stand off region of said first conductivity over said common conduction region and said charge compensation region;
a base region of said second conductivity over said stand off region;
a source region of said first conductivity over said base region.
14. The superjunction semiconductor device of claim 10 , further comprising a gate trench disposed in a stand off region.
15. A superjunction semiconductor device comprising:
a common conduction region of a first conductivity disposed over a substrate;
a charge compensation region of a second conductivity adjacent said common conduction region, said common conduction region comprising a first conductive region and a second conductive region formed on said first conductive region, the first and second conductive regions having different doping profiles; and
a pillar of a growth inhibition material disposed under said charge compensation region, said pillar rising above said first conductive region.
16. The superjunction semiconductor device of claim 15 , wherein said charge compensation region comprises laterally grown semiconductor material.
17. The superjunction semiconductor device of claim 15 , wherein said charge compensation region comprises at least two epitaxially grown bodies meeting at a defect region.
18. The superjunction semiconductor device of claim 15 , wherein said common conduction region, said charge compensation region, and a stand off region comprise a respective III-nitride material.
19. The superjunction semiconductor device of claim 15 , wherein said first conductive region has a higher conductivity than said second conductive region.
20. The superjunction semiconductor device of claim 15 , further comprising:
a stand off region of said first conductivity over said common conduction region and said charge compensation region;
a base region of said second conductivity over said stand off region;
a source region of said first conductivity over said base region.