Method and system of reducing power consumption of system on chip based on analog-to-digital control circuitry
Methods and system of reducing power consumption of system on chip based on analog-to-digital control circuitry are disclosed. In one embodiment, a method includes converting an analog signal of external device coupled to the system on chip to a digital signal using an analog-to-digital converter (ADC) of the system on chip with a processor of the system on chip in a sleep mode or power down mode. The method further includes waking up the processor of the system on ship to perform an exception event based on a comparison of the digital signal with a threshold value associated with the external device.
1 . A method for reducing power consumption of a system on chip, comprising:
receiving a signal from an external device coupled to the system on chip;
measuring the signal while a processor of the system on chip is in a sleep mode or power down mode; and
waking up the processor of the system on chip based on a comparison of the signal with a threshold value associated with the external device, wherein the threshold value is stored to a memory of the system on chip.
2 . The method of claim 1 , wherein the external device comprises a sensor device.
3 . The method of claim 1 , wherein the measuring the signal comprises converting the signal from analog data to digital data using an analog-to-digital converter (ADC).
4 . The method of claim 3 , wherein the comparison of the signal with the threshold value comprises periodically comparing the digital data with the threshold value.
5 . The method of claim 1 , wherein the waking up the processor comprises storing the signal to a buffer of the system on chip.
6 . The method of claim 5 , further comprising performing an exception event based on the signal to the buffer of the system on chip.
7 . The method of claim 1 in a form of a machine-readable medium embodying a set of instructions that, when executed by a machine, causes the machine to perform the method of claim 1 .
8 . A method for reducing power consumption of a system on chip, comprising:
converting an analog signal of an external device coupled to the system on chip to a digital signal using an analog-to-digital converter (ADC) of the system on chip with a processor of the system on chip in a sleep mode or power down mode; and
waking up the processor of the system on chip to perform an exception event based on a comparison of the digital signal with a threshold value associated with the external device.
9 . The method of claim 8 , wherein the converting the analog signal comprises turning on power of the ADC instances before the converting the analog signal to the digital signal.
10 . The method of claim 9 , wherein the converting the analog signal further comprises turning off the power of the ADC after the converting the analog signal to the digital signal.
11 . The method of claim 8 , wherein the converting the analog signal comprises selecting a clock associated with the ADC to control a speed of the converting the analog signal to the digital signal.
12 . The method of claim 8 , wherein the exception event comprises at least one of reporting a status of the external device to a host server coupled to the system on chip and executing a corrective action directed to the external device.
13 . A system for reducing power consumption of a system on chip, comprising:
an analog-to-digital converter (ADC) to convert an analog signal of an external device to a digital signal with a processor of the system on chip in a sleep mode or power down mode;
a comparator module to compare the digital signal to a threshold value associated with the external device; and
a finite state machine controlling the ADC to communicate a wake-up signal to the processor of the system on chip when the digital signal crosses the threshold value.
14 . The system of claim 13 , further comprising a buffer to store the digital signal obtained when the digital signal crosses the threshold value.
15 . The system of claim 14 , wherein the processor performs an exception event based on the digital signal.
16 . The system of claim 13 , further comprising a register to store a period of waking up the ADC.
17 . The system of claim 13 , wherein the ADC is controlled by the finite state machine based on control data.
18 . The system of claim 17 , wherein the control data comprises at least one of a single measurement mode and a periodic measurement mode of the ADC.
19 . The system of claim 13 , further comprising a plurality of clock oscillators to control a speed of the ADC.
20 . The system of claim 13 , wherein a voltage reference of the system comprises at least one of a bandgap voltage and the power supply voltage.