High-bandwidth interconnect network for an integrated circuit
View Patent ↗A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.
1. A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure comprising:
a first network of pipeline registers including a first plurality of pipeline registers, a second plurality of pipeline registers, and a third plurality of pipeline registers;
first one or more connectors selectively joining a first select circuit to the first plurality of pipeline registers responsive to at least one first select signal, the first select circuit including a first plurality of logic circuits and a first plurality of special-purpose circuits;
second one or more connectors selectively joining the first plurality of pipeline registers to the second plurality of pipeline registers responsive to at least one second select signal;
third one or more connectors selectively joining the second plurality of pipeline registers to the third plurality of pipeline registers responsive to at least one third select signal; and
fourth one or more connectors selectively joining the third plurality of pipeline registers to a second select circuit responsive to at least one fourth select signal, the second select circuit including a second plurality of logic circuits and a second plurality of special-purpose circuits.
2. The bus structure as recited in claim 1 , wherein the first one or more connectors comprise input converting circuitry.
3. The bus structure as recited in claim 2 , wherein the input converting circuitry comprises data zeroing circuitry.
4. The bus structure as recited in claim 2 , wherein the input converting circuitry comprises byte shuffling circuitry.
5. The bus structure as recited in claim 2 , wherein the input converting circuitry comprises latency padding circuitry.
6. The bus structure as recited in claim 2 , wherein the input converting circuitry comprises serializing circuitry.
7. The bus structure as recited in claim 1 , wherein the input converting circuitry comprises parity checking and generation circuitry.
8. The bus structure as recited in claim 1 , wherein the fourth one or more connectors comprise output converting circuitry.
9. The bus structure as recited in claim 8 , wherein the output converting circuitry comprises parity checking and generation circuitry.
10. The bus structure as recited in claim 8 , wherein the output converting circuitry comprises byte shuffling circuitry.
11. The bus structure as recited in claim 8 , wherein the output converting circuitry comprises latency padding circuitry.
12. The bus structure as recited in claim 8 , wherein the output converting circuitry comprises deserializing circuitry.
13. The bus structure as recited in claim 1 , further comprising a second network of pipeline registers and crossbar connectors joining portions of the integrated circuit, the second network of pipeline registers connectable to the first network of pipeline registers through one or more of the first, second, third, and fourth connectors.
14. The bus structure of claim 1 , wherein the first one or more connectors comprise a plurality of first bus connectors, the second one or more connectors comprise a plurality of second bus connectors, the third one or more connectors comprise a plurality of third bus connectors, and the fourth one or more connectors comprise a plurality of fourth bus connectors.
15. The bus structure of claim 1 , wherein the first plurality of pipeline registers are the same as the second plurality of pipeline registers.
16. The bus structure of claim 1 , wherein the first plurality of pipeline registers are different from the second plurality of pipeline registers.
17. The bus structure of claim 1 , wherein the first plurality of logic circuits are the same as the second plurality of logic circuits.
18. The bus structure of claim 1 , wherein the first plurality of logic circuits are different from the second plurality of logic circuits.
19. The bus structure of claim 1 , wherein the first plurality of special circuits are the same as the second plurality of special circuits.
20. The bus structure of claim 1 , wherein the first plurality of special circuits are different from the second plurality of special circuits.
21. The bus structure of claim 1 , wherein the first one or more connectors comprise a first plurality of multiplexers, the second one or more connectors comprise a second plurality of multiplexers, the third one or more connectors comprise a third plurality of multiplexers, and the fourth one or more connectors comprise a fourth plurality of multiplexers.