IP Library Granted Patent US 7,619,696
Granted Patent B2
US 7,619,696 · App. 11/902,831 · Granted Nov 17, 2009

Liquid crystal display panel

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Quick Facts
Patent No.
US 7,619,696
App. No.
11/902,831
Granted
Nov 17, 2009
Kind
B2
Abstract

In an active matrix type liquid crystal display panel of the invention, an inner shorting line that is thicker than the scan lines and picture lines is disposed so as to surround the periphery of a display area included in the liquid crystal display panel; the scan lines are each connected to first electrostatic prevention circuits and bundled by a first shorting wire; the first shorting wire is connected to the inner shorting line via at least one among second electrostatic prevention circuits; a common potential line that is thicker than the inner shorting line is disposed around the outer periphery of the inner shorting line; and at least one connection is provided between the inner shorting line and common potential line, electrically connecting each to the other.

Claims (25)

1. A liquid crystal display panel, comprising:

an array substrate in which pixels are constituted by disposing a pixel electrode and a thin film transistor in each area enclosed by scan lines and picture lines arrayed as a matrix, and

a color filter substrate equipped with a common electrode;

wherein an inner shorting line that is thicker than the scan lines and picture lines is disposed so as to surround the periphery of a display area included in the liquid crystal display panel,

wherein the scan lines are each connected to first electrostatic prevention circuits and are bundled by a first shorting wire,

wherein the first shorting wire is connected to the inner shorting line via at least one second electrostatic prevention circuit,

wherein a common potential line that is thicker than the inner shorting line is disposed around the outer periphery of the inner shorting line, and

wherein at least one connection is provided between the inner shorting line and the common potential line, electrically connecting the inner shorting line and the common potential line.

2. The liquid crystal display panel according to claim 1 , wherein the picture lines are each connected to third electrostatic prevention circuits and are bundled by a second shorting wire, the second shorting wire being connected to the inner shorting line via fourth electrostatic prevention circuits.

3. The liquid crystal display panel according to claim 1 , wherein the first and second electrostatic prevention circuits each include a pair of diodes connected in parallel with an anode of each connected to a cathode of the other, or each include parallel circuits in which a pair of transistors with short circuits created between gates and sources thereof are connected in opposite orientations to each other.

4. The liquid crystal display panel according to claim 2 , wherein the third and fourth electrostatic prevention circuits each include a pair of diodes connected in parallel with an anode of each connected to a cathode of the other, or each include parallel circuits in which a pair of transistors with short circuits created between a gates and sources thereof are connected in opposite orientations to each other.

5. A liquid crystal display panel, comprising:

an array substrate in which pixels are constituted by disposing a pixel electrode and a thin film transistor in each area enclosed by scan lines and picture lines arrayed as a matrix, and

a color filter substrate equipped with a common electrode;

wherein an inner shorting line that is thicker than the scan lines and picture lines is disposed so as to surround the periphery of a display area included in the liquid crystal display panel,

wherein the scan lines are each connected to first electrostatic prevention circuits and are bundled by a first shorting wire,

wherein the first shorting wire is connected to the inner shorting line via at least one second electrostatic prevention circuit,

wherein a common potential line that is thicker than the inner shorting line is disposed around the outer periphery of the inner shorting line,

wherein at least one group of multiple contact holes parallel with the common potential line is provided on an insulator provided over the inner shorting line,

wherein at least one group of multiple contact holes parallel with the inner shorting line is provided on an insulator provided over the common potential line, and

wherein the inner shorting line and common potential lines are electrically connected by the contact holes and by conductive films provided over the insulators.

6. The liquid crystal display panel according to claim 5 , wherein the contact holes are slits that extend in parallel with the inner shorting line or the common potential line.

7. The liquid crystal display panel according to claim 5 , wherein the picture lines are each connected to third electrostatic protection circuits and are bundled by a second shorting wire, the second shorting wire being connected to the inner shorting line via fourth electrostatic prevention circuits.

8. The liquid crystal display panel according to claim 5 , wherein the first and second electrostatic prevention circuits each include a pair of diodes connected in parallel with an anode of each connected to a cathode of the other, or each include parallel circuits in which a pair of transistors with short circuits created between gates and sources thereof are connected in opposite orientations to each other.

9. The liquid crystal display panel according to claim 7 , wherein the third and fourth electrostatic prevention circuits each include a pair of diodes connected in parallel with an anode of each connected to a cathode of the other, or each include parallel circuits in which a pair of transistors with short circuits created between gates and sources thereof are connected in opposite orientations to each other.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 11, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072398/0001 →
MERGER AND CHANGE OF NAME Recorded Jul 24, 2025
From: JAPAN DISPLAY EAST INC.; JAPAN DISPLAY WEST INC.
To: JAPAN DISPLAY INC.
Reel/Frame 071935/0063 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 8, 2013
From: SONY CORPORATION
To: JAPAN DISPLAY WEST INC.
Reel/Frame 031378/0243 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 11, 2011
From: EPSON IMAGING DEVICES CORPORATION
To: SONY CORPORATION
Reel/Frame 025935/0327 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2007
From: OTA, AKIO
To: EPSON IMAGING DEVICES CORPORATION
Reel/Frame 019946/0280 →