Computing system capable of parallelizing the operation of multiple graphics pipelines (GPPLS) implemented on a multi-core CPU chip

1 . A computing system capable of parallelizing the operation of multiple graphics pipelines (GPPLs) implemented on a multi-core CPU chip, said computing system comprising:

CPU memory space for storing one or more graphics-based applications and a graphics library for generating graphics commands and data (GCAD) during the execution of said graphics-based application;

a multi-core CPU chip having multiple CPU-cores and an interconnect network;

a bridge circuit for operably connecting said CPU memory space and said multi-core CPU chip;

a multi-mode parallel graphics rendering subsystem supporting multiple modes of parallel operation selected from the group consisting of object division, image division, and time division, and wherein each mode of parallel operation includes at least three stages, namely, decomposition, distribution and recomposition; and

a plurality of graphic processing pipelines (GPPLs), implemented using some of said CPU-cores, and supporting a parallel graphics rendering process that employs one or more of said object division, image division and/or time division modes of parallel operation in order to execute graphic commands, process graphics data, and render pixel-composited images containing graphics for display on a display device during the run-time of said graphics-based application, and said display device being connectable to said bridge circuit by way of a data communication interface, or to a external graphics card connected to the interconnect network of said multi-core CPU chip.

2 . The computing system of claim 1 , which further comprises:

an automatic mode control module for automatically controlling the mode of parallel operation of said multi-mode parallel graphics rendering subsystem during the run-time of said graphics-based application, so that said GPPLs are driven in a parallelized manner during the run-time of said graphics-based application.

3 . The computing system of claim 2 , wherein said multi-mode parallel graphics rendering subsystem further includes:

(i) first and second decomposition submodules for supporting the decomposition stage of parallel operation;

(ii) a distribution module for supporting the distribution stage of parallel operation; and

(iii) a recomposition module for supporting the recomposition stage of parallel operation.

4 . The computing system of claim 3 , wherein during operation,

(i) said first decomposition submodule divides the stream of graphic commands and data according to the required parallelization mode, operative at any instant in time;

(ii) said second decomposition submodule receives the stream of graphic commands and data from said first decomposition submodule;

(iii) said distribution module uses said interconnect network to distribute graphic commands and data to said multiple GPUs,

(iv) said recomposition module uses said interconnect network to transfer composited pixel data between said recomposition module and said multiple GPUs during said recomposition stage, and

(v) finally recomposited pixel data sets are displayed as graphical images on said display device.

5 . The computing system of claim 2 , wherein said automatic mode control module employs profiling of scenes in said graphics-based application.

6 . The computing system of claim 5 , wherein said profiling of scenes in said graphics-based application, is carried out in real-time during run-time of said graphics-based application.

7 . The computing system of claim 6 , wherein said real-time profiling of scenes in said graphics-based application involves (i) collecting and analyzing performance data associated with said multi-mode parallel graphics rendering subsystem and said computing system, during application run-time, (ii) constructing scene profiles for the image frames associated with particular scenes in said particular graphics-based application, and (iii) maintaining said scene profiles in a application/scene profile database that is accessible to said automatic mode control module during run-time, so that during the run-time of said graphics-based application, said automatic mode control module can access and use said scene profiles maintained in said application/scene profile database and determine how to dynamically control the modes of parallel operation of said multi-mode parallel graphics rendering subsystem to optimize system performance.

8 . The computing system of claim 5 , wherein said automatic mode control module employs real-time detection of scene profile indices programmed within pre-profiled scenes of said graphics-based application;

wherein said pre-profiled scenes are analyzed prior to run-time, and indexed with said scene profile indices; and

wherein and mode control parameters (MCPS) corresponding to said scene profile indices, are stored within an application/scene profile database accessible to said automatic mode control module during application run-time.

9 . The computing system of claim 8 , wherein during run-time, said automatic mode control module automatically detects said scene profile indices and uses said detected said scene profile indices to access corresponding MCPs from said application/scene profile database so as to determine how to dynamically control the modes of parallel operation of said multi-mode parallel graphics rendering subsystem to optimize system performance.

10 . The computing system of claim 5 , wherein said automatic mode control module employs real-time detection of mode control commands (MCCs) programmed within pre-profiled scenes of said graphics-based application;

wherein said pre-profiled scenes are analyzed prior to run-time, and said MCCs are directly programmed within the individual image frames of each scene; and

wherein during run-time, said automatic mode control module automatically detects said MCCs along the graphics command and data stream, and uses said MCCs so as to determine how to dynamically control the modes of parallel operation of said multi-mode parallel graphics rendering subsystem to optimize system performance.

11 . The computing system of claim 2 , wherein said automatic mode control module employs a user interaction detection (UID) mechanism for real-time detection of the user's interaction with said computing system.

12 . The computing system of claim 11 , wherein, in conjunction with said scene profiling, said automatic mode control module also uses said UID mechanism to determine how to dynamically control the modes of parallel operation of the multi-mode parallel graphics rendering subsystem to optimize system performance, at any instance in time during the run-time of said graphics-based application.

13 . The computing system of claim 1 , wherein said bridge circuit is a North memory bridge circuit disposed between said CPU memory space and said one or more CPUs.

14 . The computing system of claim 1 , wherein said display device is a device selected from the group consisting of an flat-type display panel, a projection-type display panel, and other image display devices.

15 . The computing system of claim 1 , wherein said computing system is a machine selected from the group consisting of a PC-level computer, information server, laptop, game console system, portable computing system, and any computational-based machine supporting the real-time generation and display of 3D graphics.

16 . The computing system of claim 2 , wherein said automatic mode control module and said first decomposition submodule are each implemented as a software package in said CPU memory space; and wherein said second decomposition submodule, said distribution module and said recomposition module are each implemented within said multi-core CPU chip, and are in operable communication with said automatic mode control module in said CPU memory space by way of said interconnect network and said bridge circuit.

17 . The computing system of claim 16 , wherein said each said software package is implemented in said CPU memory space.

18 . The computing system of claim 4 , wherein only one of said GPUs is designated as the primary GPU and is responsible for driving said display unit with a final pixel image composited within a frame buffer (FB) maintained by said primary GPU, and all other GPUs function as secondary GPUs, supporting the pixel image recompositing process.