Wireless receiver apparatus provided with gain control amplifier

1. A wireless receiver apparatus comprising:

a gain control amplifier for controlling a gain of a reception signal, and

a maintaining device for compulsorily maintaining the gain of the gain control amplifier at a predetermined fixed value only in a predetermined specified interval,

wherein a start timing of the specified interval is determined by an edge of a predetermined timer start signal, and

wherein a duration of the specified interval is determined on the basis of a count of a predetermined timer clock signal and a count of a predetermined timer count set bus signal.

2. The wireless receiver apparatus as claimed in claim 1 ,

wherein the maintaining device comprises a latch circuit for maintaining a gain set value immediately prior to the specified interval.

3. The wireless receiver apparatus as claimed in claim 1 ,

wherein an end timing of the specified interval is determined on the basis of an edge of a predetermined timer reset signal.

4. The wireless receiver apparatus as claimed in claim 3 , further comprising a second selection circuit for selecting one second control signal from a plurality of predetermined second control signals, and outputting a selected signal as the timer reset signal.

5. The wireless receiver apparatus as claimed in claim 1 , further comprising a setting device for setting whether or not to operate the maintaining device on the basis of a predetermined AGC timer busy/non-busy signal.

6. The wireless receiver apparatus as claimed in claim 5 ,

wherein the AGC timer busy/non-busy signal is transmitted on a predetermined three-line bus for setting a predetermined reception channel.

7. The wireless receiver apparatus as claimed in claim 1 , further comprising a first selection circuit for selecting one first control signal from a plurality of predetermined first control signals, and outputting a selected signal as the timer start signal.

8. The wireless receiver apparatus as claimed in claim 1 , further comprising a frequency divider circuit for dividing a frequency of a predetermined reference clock signal by an inputted frequency division number, and outputting a frequency-divided signal as the timer clock signal.

9. The wireless receiver apparatus as claimed in claim 8 , further comprising a fourth selection circuit for selecting one signal from a serial timer clock set bus signal transmitted on a three-line bus for setting a predetermined reception channel and an external timer clock set bus signal, and outputting a selected signal as a signal representing the frequency division number.

10. The wireless receiver apparatus as claimed in claim 1 , further comprising a third selection circuit for selecting one signal from a serial timer count set bus signal transmitted on a three-line bus for setting a predetermined reception channel and an external timer count set bus signal, and outputting a selected signal as the timer count set bus signal.

11. The wireless receiver apparatus as claimed in claim 10 , further comprising a further setting device for setting timer counts of the serial timer count set bus signal and the external timer count set bus signal to arbitrary timer counts, respectively.

12. The wireless receiver apparatus as claimed in claim 1 ,

wherein the start timing of the specified interval is set for an interval for which a unique word (UW) of a received wireless signal is received.

13. The wireless receiver apparatus as claimed in claim 1 ,

wherein an end timing of the specified interval is set after transfer of reception data in one slot of a received wireless signal is completed.

14. A semiconductor integrated circuit which is formed by integrating a circuit of a wireless receiver apparatus, said integrated circuit comprising:

a gain control amplifier for controlling a gain of a reception signal, and

a maintaining device for compulsorily maintaining the gain of the gain control amplifier at a predetermined fixed value only in a predetermined specified interval,

wherein a start timing of the specified interval is determined by an edge of a predetermined timer start signal, and

wherein a duration of the specified interval is determined on the basis of a count of a predetermined timer clock signal and a count of a predetermined timer count set bus signal.