Pre-driver circuit and appparatus using same
View Patent ↗In one embodiment, a pre-driver circuit comprises input circuitry connected to receive a digital input signal that alternates between an upper voltage rail and a lower voltage rail and to provide a first inverted signal that is an inversion of the digital input signal and a second inverted signal that is an inversion of the first inverted signal. The pre-driver circuit also includes actuation circuitry connected to be driven by the digital input signal, the first inverted signal, and the second inverted signal to produce a digital output signal that alternates between an upper limit that is less than the upper rail and a lower limit that is greater than the lower rail by at least an amount, wherein all transistors forming the actuation circuitry comprise a single channel type.
1. A digital circuit, comprising:
input circuitry connected to receive a digital input signal that alternates between an upper voltage rail and a lower voltage rail and to provide a first inverted signal that is an inversion of said digital input signal and a second inverted signal that is an inversion of said first inverted signal; and
actuation circuitry connected to be driven by said digital input signal, said first inverted signal, and said second inverted signal to produce a digital output signal that alternates between an upper limit that is less than said upper rail and a lower limit that is greater than said lower rail by at least an amount, wherein all transistors forming said actuation circuitry comprise a single channel type.
2. The digital circuit according to claim 1 , wherein said actuation circuitry comprises a first stack of transistors and a second stack of transistors coupled together to drive said digital output signal.
3. The digital circuit according to claim 2 , wherein a first transistor of said first stack of transistors is connected to be driven by said first inverted signal and a second transistor of said first stack of transistors is connected to be driven by said digital input signal.
4. The digital circuit according to claim 3 , wherein the difference between said upper limit and said upper rail is determined based on the threshold voltage of said first transistor of said first stack of transistors.
5. The digital circuit according to claim 3 , wherein a first transistor of said second stack of transistors is connected to be driven by said second inverted signal and a second transistor of said second stack of transistors is connected to be driven by said digital output signal.
6. The digital circuit according to claim 5 , wherein the difference between said lower limit and said lower rail is determined based on a ratio of the strengths of said second transistor of said first stack and said first transistor of said second stack.
7. The digital circuit according to claim 1 , wherein said single channel type is n-channel.
8. The digital circuit according to claim 1 , wherein said single channel type is p-channel.