III-nitride device with reduced piezoelectric polarization
View Patent ↗A III-nitride based field effect transistor obtains improved performance characteristics through manipulation of the relationship between the in-plane lattice constant of the interface of material layers. A high mobility two dimensional electron gas generated at the interface of the III-nitride materials permits high current conduction with low ON resistance, and is controllable through the manipulation of spontaneous polarization fields obtained according to the characteristics of the III-nitride material. The field effect transistor produced can be made to be a nominally on device where the in-plane lattice constants of the material forming the interface match. A nominally off device may be produced where one of the material layers has an in-plane lattice constant that is larger than that of the other layer material. The layer materials are preferably InAlGaN/GaN layers that are particularly tailored to the characteristics of the present invention.
1. A III-nitride device, comprising: a first layer composed of a first III-nitride material having a first composition; a second layer composed of a second III-nitride material forming a heterojunction with said first layer, said second layer having a composition different from the first composition to generate a two dimensional electron gas with said first layer, and a lattice constant in the plane of the heterojunction of the first and second layers that is approximately the same as the lattice constant of the first layer in the plane of the heterojunction between the first and the second layers.
2. A device according to claim 1 , wherein one of the first or second III-nitride material is comprised of GaN.
3. A device according to claim 2 , wherein the other of the first or second III-nitride material is comprised of InAlGaN.
4. A device according to claim 2 , wherein the GaN material has a bandgap that is less than that of the other of the first or second III-nitride materials.
5. A device according to claim 3 , wherein the InAlGaN material has a bandgap that is greater than that of the GaN material.
6. A device according to claim 1 , wherein the first III-nitride material and the second III-nitride material have different bandgaps.
7. A device according to claim 1 , further comprising a drain electrode, a source electrode and a gate electrode positioned between the source and the drain electrodes.
8. A device according to claim 7 , wherein the thickness of semiconductor under said source and drain electrodes is different from the thickness of said semiconductor under said gate electrode.
9. A III-nitride device, comprising: a first layer composed of a first III-nitride material having a first composition; and a second layer composed of a second III-nitride material having a second composition different from the first composition, the second layer being disposed on the first layer to form a heterojunction with the first layer, the heterojunction having a piezoelectric polarization lower than an AlGaN/GaN heterojunction piezoelectric polarization.
10. A device according to claim 9 , wherein the bandgap for one of the first or second III-nitride materials is greater that than of the other.
11. A device according to claim 9 , wherein one of the first or second III-nitride material is comprised of GaN.
12. A device according to claim 11 , wherein the other of the first or second III-nitride material is comprised of InAlGaN.
13. A device according to claim 11 , wherein the GaN material has a bandgap that is less than that of the other of the first or second III-nitride materials.
14. A device according to claim 12 , wherein the InAlGaN material has a bandgap that is greater than that of the GaN material.
15. A device according to claim 9 , wherein the first III-nitride material and the second III-nitride material have different bandgaps.
16. A device according to claim 9 , further comprising a drain electrode, a source electrode and a gate electrode positioned between the source and the drain electrodes.
17. A device according to claim 16 , wherein the thickness of semiconductor under said source and drain electrodes is different from the thickness of said semiconductor under said gate electrode.